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NCP5008DMR2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
NCP5008, NCP5009
http://onsemi.com
7
Figure 9. Load Current (I
led
) vs. I
ref
@ V
bat
= 3.6 V, V
load
= 15 V and 10 V
0
5
10
15
20
25
30
35
40
45
50
0 10203040506070
I
ref
(mA)
Figure 10. Inductor Peak Current Error vs.
Theoretical Inductor Peak Current
0
2
4
6
8
10
12
14
16
18
20
0 50 100 150 200 250 300 350 40
0
Figure 11. Inductor Peak Current vs. I
photo
@ I
ref
= 34 mA
0
20
40
60
80
100
120
140
160
180
200
0 10203040
Figure 12. Stand by Current vs. V
bat
@ T = 20°C
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6
I
LED
(mA)
V
load
= 10 V
V
load
= 15 V
I
photo
(mA)
I
peak
(mA)
THEORETICAL I
peak
(mA)
I
peak
ERROR (%)
V
bat
(V)
6
.0
TYPICAL OPERATING CHARACTERISTICS
Condition: Typical Application: L = 22 mH, Cin = 10 mF, Cout = 2.2 mF, R1 = 30 kW
Theoretical
Measured
I
stby
(mA)
50
55
60
65
70
75
80
0 5 10 15 20 25 30
35
EFFICIENCY (%)
I
LED
(mA)
85
Figure 13. Efficiency vs. Load Current @ 4 LEDS
(V
load
= 4*Vf ⇒ 14.2 V)
Figure 14. Efficiency vs. Load Current @ 3 LEDS
(V
load
= 3*Vf ⇒ 10.5 V)
50
55
60
65
70
75
80
0 5 10 15 20 25 30 35
EFFICIENCY (%)
V
bat
= 3.6 V
V
bat
= 4.2 V
V
bat
= 3.0 V
I
LED
(mA)
V
bat
= 3.6 V
V
bat
= 4.2 V
V
bat
= 3.0 V
NCP5008, NCP5009
http://onsemi.com
8
70
75
80
85
90
95
100
0102030405060
70
EFFICIENCY (%)
V
bat
= 6.0 V
I
LED
(mA)
60
65
70
75
80
85
90
0 5 10 15 20 25 30 35
EFFICIENCY (%)
I
LED
(mA)
Figure 15. Efficiency vs Load Current @ 2 LEDS
(V
load
= 2*Vf ⇒ 7.1 V)
Figure 16. Efficiency vs Load Current @ 4 LEDS
(V
load
= 2 strings of 2 LEDs in series = 7.1 V)
5.0 V
4.2 V
3.6 V
3.0 V
V
bat
= 3.6 V
V
bat
= 4.2 V
V
bat
= 3.0 V
TYPICAL OPERATING CHARACTERISTICS
Condition: Typical Application: L = 22 mH, Cin = 10 mF, Cout = 2.2 mF, R1 = 30 kW
Operating Description
Figure 17. Digital Timing Definitions
90%
50%
10%
t
CLKmin
tf tr
Figure 18. Typical Schmitt Trigger Characteristic
V
bat
ON
OFF
Output
0.30* V
bat
0.70* V
bat
V
bat
Input
Input Schmitt Triggers
All the Logic Input pins have built−in Schmitt trigger
circuits to prevent the NCP5008/NCP5009 against
uncontrolled operation. The typical dynamic characteristics
of the related pins are depicted in Figure 18.
The output signal is guaranteed to go High when the
input voltage is above 0.70*V
bat
, and will go Low when the
input voltage is below 0.30*V
bat
.
Local Mode
When the system operate in a Local Mode (Pin 6,
/LOCAL=Low), the output current depends solely upon
the current drawn pin 1. The clock signal is irrelevant and
the output current is derived by equation I
out
= I
ref
* k, the
internal constant k being equal to 746.
ESD Protection
The NCP5008/NCP5009 includes silicon devices to
protect the pins against the ESD spikes voltages. To cope
with the different ESD voltages developed in the
applications, the built−in structures have been designed to
handle $2.0 kV in Human Body Model (HBM) and
$200 V in Machine Model (MM) and on each pin.
NCP5008, NCP5009
http://onsemi.com
9
Remote Control Programming Sequence
Figure 19. Programming Sequence
I
out
ref
Iout
B7
B6
B5
B4
B3
B2
B1
Qdata
CLK
CLEAR
CS
tCSsetup
tclear
Last Latched Bit
Output Current Programmed Register
Internal Latch Data and Reset
Ioutdly
Upon CS transition from High to Low, the internal
sequence will take place:
− Qdata is internally set to high level.
− Upon positive going transition of the next CLK signal,
the Qdata is shifted to the next Bn stage.
− Clear the Qdata flip−flop upon the positive going of
the SetReg[B1] transient.
The sequence keeps going until CS = High.
When the CS line returns to a High state, the
programming output current flip−flop is set according to
the previous state of the shift register and SetReg B[1−7] is
cleared afterward.
Depending upon the CS width, for a given CLK period,
the last SetReg bit will be latched and the output current
will be adjusted accordingly. If the number of CLK pulses
is higher than 7, the Qdata is lost and the SetReg register
bits B[1−7] are in the Low state, yielding a zero output
current.
The internal shift register can be clear by sending more
than 7 pulses to the CLK pin when the pin CS is low. If the
internal shift register is clear upon the CS transition from
Low to High, the device will be placed or maintained in the
shut down mode.
When the register content is higher than zero, the DC/DC
is activated and a 100 ms delay (typical) is necessary to
stabilize the output current to the programmed value.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

NCP5008DMR2

Mfr. #:
Buy NCP5008DMR2
Manufacturer:
ON Semiconductor
Description:
IC LED DRIVER RGLTR 75MA 10MICRO
Lifecycle:
New from this manufacturer.
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