LTC6401-20
15
640120f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
3.00 ± 0.10
(4 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.45 ± 0.05
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.45 ± 0.10
(4-SIDES)
0.75 ± 0.05
R = 0.115
TYP
0.25 ± 0.05
1
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
15 16
2
0.50 BSC
0.200 REF
2.10 ± 0.05
3.50 ± 0.05
0.70 ±0.05
0.00 – 0.05
(UD16) QFN 0904
0.25 ±0.05
0.50 BSC
PACKAGE
OUTLINE
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
TYPICAL APPLICATION
Test Circuit B, 4-Port Analysis
0.1μF
13
640120 TA02
1
V
+
2
V
OCM
14
7
15
+OUT
+OUTF
–OUTF
–OUT
+IN
IN+ OUT–
IN– OUT+
+IN
–IN
–IN
516
R
G
100Ω
R
OUT
12.5Ω
R
F
1000Ω
R
G
100Ω
R
F
1000Ω
6
4
V
–
3
V
+
V
OCM
V
+
V
+
12
V
–
11
ENABLE
9
V
–
10
V
+
COMMON
MODE CONTROL
1/2
AGILENT
E5O71A
BIAS CONTROL
8
R
OUT
12.5Ω
37.4Ω
37.4Ω
R
FILT
50Ω
R
FILT
50Ω
C
FILT
1.7pF
1000pF
0.1μF
0.1μF
0.1μF
PORT 3
(50Ω)
PORT 4
(50Ω)
1/2
AGILENT
E5O71A
200Ω
0.1μF
0.1μF
PORT 1
(50Ω)
PORT 2
(50Ω)
0.1μF
1000pF
