AD626
–10–
necessary to min i mize gain error. Also, any mis match be tween the
total source re sis tance at each input will af fect gain ac cu ra cy and
common -mode rejection (CMR). For ex am ple: when operating at
a gain of 10, an 80 ⍀ mismatch in the source re sis tance between
the inputs will degrade CMR to 68 dB.
The output buffer, A2, operates at a gain of 2 or 20, thus setting
the overall, precalibrated gain of the AD626 (with no ex ter nal
com po nents) at 10 or 100. The gain is set by the feedback net work
around amplifi er A2.
The output of amplifi er A2 relies on a 10 k⍀ resistor to –V
S
for
“pull-down.” For single-supply operation, (–V
S
= “GND”), A2
can drive a 10 k⍀ ground ref er enced load to at least +4.7 V. The
min i mum, nominally “zero,” output voltage will be 30 mV. For
dual-supply op er a tion (±5 V), the positive output voltage swing
will be the same as for a single supply. The negative swing will be
to –2.5 V, at G = 100, limited by the ratio:
–V
RR
RRR
S
×
+
++
15 14
13 14 15
The negative range can be extended to –3.3 V (G = 100) and –4 V
(G = 10) by add ing an external 10 k⍀ pull-down from the out put
to –V
S
. This will add 0.5 mA to the AD626’s qui es cent cur rent,
bringing the total to 2 mA.
The AD626’s 100 kHz bandwidth at G = 10 and 100 (a 10 MHz
gain bandwidth) is much higher than can be obtained with low
power op amps in discrete dif fer en tial amplifi er circuits. Fur ther -
more, the AD626 is stable driving capacitive loads up to 50 pF
(G10) or 200 pF (G100). Capacitive load drive can be increased
to 200 pF (G10) by connecting a 100 ⍀ resistor in series with the
AD626’s output and the load.
ADJUSTING THE GAIN OF THE AD626
The AD626 is easily confi gured for gains of 10 or 100. Figure 5
shows that for a gain of 10, Pin 7 is simply left un con nect ed; simi-
larly, for a gain of 100, Pin 7 is grounded, as shown in Fig ure 6.
Gains between 10 and 100 are easily set by connecting a vari able
resistance between Pin 7 and Analog GND, as shown in Fig ure 7.
Because the on-chip resistors have an absolute tol er ance of ±20%
(although they are ratio matched to within 0.1%), at least a 20%
adjustment range must be provided. The values shown in the
table in Figure 7 provide a good trade-off be tween gain set range
and resolution, for gains from 11 to 90.
0.1F
OUTPUT
+V
S
NOT
CONNECTED
+INPUT
–INPUT
0.1F
1
2
3
4
8
7
6
5
–IN
+IN
G = 10
OUT
AD626
200k⍀ 200k⍀
100k⍀
G = 2
ANALOG
GND
–V
S
FILTER
1/6
+V
S
–V
S
G = 30
Figure 5. AD626 Confi gured for a Gain of 10
0.1F
OUTPUT
+INPUT
–INPUT
0.1F
1
2
3
4
8
7
6
5
–IN
+IN
G = 100
OUT
AD626
200k⍀ 200k⍀
100k⍀
ANALOG
GND
–V
S
FILTER
1/6
+V
S
+V
S
–V
S
G = 30
G = 2
Figure 6. AD626 Confi gured for a Gain of 100
R
G
R
H
CF
FILTER
(OPTIONAL)
OUTPUT
+V
S
+INPUT
–INPUT
0.1F
1
2
3
4
8
7
6
5
–IN
+IN
G = 100
OUT
AD626
200k⍀ 200k⍀
100k⍀
ANALOG
GND
–V
S
FILTER
1/6
+V
S
CORNER FREQUENCY OF FILTER =
1
2CF (100k⍀)
GAIN RANGE R
G
(⍀) R
H
(⍀)
11 – 20
20 – 40
40 – 80
80 – 100
100k
10k
1k
100
4.99k
802
80
2
RESISTOR VALUES FOR GAIN ADJUSTMENT
0.1F
–V
S
G = 2
G = 30
Figure 7. Recommended Circuit for Gain Adjustment
SINGLE-POLE LOW-PASS FILTERING
A low-pass fi lter can be easily implemented by using the fea tures
provided by the AD626.
By simply connecting a capacitor between Pin 4 and ground,
a single-pole low-pass fi lter is created, as shown in Figure 8.
CF
CORNER FREQUENCY OF FILTER =
1
2CF (100k⍀)
OUTPUT
+10V
+INPUT
–INPUT
0.1F
1
2
3
4
8
7
6
5
–IN
+IN
G = 100
OUT
AD626
200k⍀ 200k⍀
100k⍀
ANALOG
GND
–V
S
FILTER
1/6
+V
S
G = 2
G = 30
Figure 8. A One-Pole Low-Pass Filter Circuit
Which Operates from a Single +10 V Supply
REV. D
