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5962-8771901EA

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
AD625
REV. D–12–
GROUND RETURNS FOR BIAS CURRENTS
Input bias currents are those currents necessary to bias the input
transistors of a dc amplifier. There must be a direct return path
for these currents, otherwise they will charge external capaci-
tances, causing the output to drift uncontrollably or saturate.
Therefore, when amplifying “floating” input sources such as
transformers, or ac-coupled sources, there must be a dc path
from each input to ground as shown in Figure 35.
AD625
+V
S
–V
S
R
F
R
G
R
F
V
OUT
LOAD
TO POWER
SUPPLY
GROUND
SENSE
REFERENCE
Figure 35a. Ground Returns for Bias Currents with
Transformer Coupled Inputs
AD625
+V
S
–V
S
R
F
R
G
R
F
V
OUT
LOAD
TO POWER
SUPPLY
GROUND
SENSE
REFERENCE
Figure 35b. Ground Returns for Bias Currents with
Thermocouple Input
AD625
+V
S
–V
S
R
F
R
G
R
F
V
OUT
LOAD
TO POWER
SUPPLY
GROUND
SENSE
REFERENCE
100k 100k
Figure 35c. Ground Returns for Bias Currents with AC
Coupled Inputs
AUTOZERO CIRCUITS
In many applications it is necessary to maintain high accuracy.
At room temperature, offset effects can be nulled by the use of
offset trimpots. Over the operating temperature range, however,
offset nulling becomes a problem. For these applications the
autozero circuit of Figure 36 provides a hardware solution.
OTHER CONSIDERATIONS
One of the more overlooked problems in designing ultralow-
drift dc amplifiers is thermocouple induced offset. In a circuit
comprised of two dissimilar conductors (i.e., copper, kovar), a
current flows when the two junctions are at different tempera-
tures. When this circuit is broken, a voltage known as the
“Seebeck” or thermocouple emf can be measured. Standard IC
lead material (kovar) and copper form a thermocouple with a
high thermoelectric potential (about 35 µV°C). This means that
care must be taken to insure that all connections (especially
those in the input circuit of the AD625) remain isothermal. This
includes the input leads (1, 16) and the gain sense lines (2, 15).
These pins were chosen for symmetry, helping to desensitize the
input circuit to thermal gradients. In addition, the user should
also avoid air currents over the circuitry since slowly fluctuating
AD625
+V
S
–V
S
AD7502
GND V
DD
V
SS
15 16
13
14
V
DD
V
SS
GND
AD7510DIKD
A1 A2 A3 A4
200s
ZERO PULSE
AD711
+
V
IN
–
0.1F LOW
LEAKAGE
1k
12
11
9
10
V
OUT
Figure 36. Auto-Zero Circuit
thermocouple voltages will appear as “flicker” noise. In SPGA
applications relay contacts and CMOS mux leads are both
potential sources of additional thermocouple errors.
The base emitter junction of an input transistor can rectify out
of band signals (i.e., RF interference). When amplifying small
signals, these rectified voltages act as small dc offset errors. The
AD625 allows direct access to the input transistors’ bases and
emitters enabling the user to apply some first order filtering to
these unwanted signals. In Figure 37, the RC time constant
should be chosen for desired attenuation of the interfering signals.
In the case of a resistive transducer, the capacitance alone work-
ing against the internal resistance of the transducer may suffice.
+GAIN SENSE
+IN
–IN
RTI NULL
RTI NULL
RTO
NULL
RTO
NULL
+V
+GAIN DRIVE
–GAIN DRIVE
R
F
R
G
R
F
NC
REF
–V
S
V
OUT
+V
S
A1 A2
AD625
10k
10k 10k
10k
A3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FILTER
CAP
R R
FILTER
CAP
CC
–GAIN SENSE
+IN
SENSE
V
OUT
–IN
Figure 37. Circuit to Attenuate RF Interference
AD625
REV. D
–13–
–
V
IN
+
12-BIT
DAS
10k
10k
AD625
10k
10k
V
S
–INPUT
–GAIN
SENSE
–GAIN
DRIVE
+GAIN
DRIVE
+GAIN
SENSE
+INPUT
20k
15.6k
3.9k
975k
650k
975k
3.9k
20k
15.6k
C
S
C
S
I
S
I
S
I
OUT
I
OUT
C
OUT
C
OUT
R
ON
R
ON
C
S-OUT
C
S-OUT
Figure 39. SPGA with Multiplexer Error Sources
Figure 39 shows a complete SPGA feeding a 12-bit DAS with a
0 V–10 V input range. This configuration was used in the error
budget analysis shown in Table II. The gain used for the RTI
calculations is set at 16. As the gain is changed, the ON resis-
tance of the multiplexer and the feedback resistance will change,
which will slightly alter the values in the table.
Table II. Errors Induced by Multiplexer to an SPGA
Induced Specifications Voltage Offset
Error AD625C AD7520KN Calculation Induced RTI
RTI Offset Gain Sense Switch 40 nA × 170 Ω = 6.8 µV
Voltage Offset Resistance 6.8 µV
Current 170 Ω
40 nA
RTI Offset Gain Sense Differential 60 nA × 6.8 Ω = 0.41 µV
Voltage Current Switch 0.41 µV
60 nA Resistance
6.8 Ω
RTO Offset Feedback Differential 2 (0.2 nA × 20 kΩ) 0.5 µV
Voltage Resistance Leakage = 8 µV/16
20 kΩ
1
Current (I
S
)
2
+0.2 nA
–0.2 nA
RTO Offset Feedback Differential 2 (1 nA × 20 kΩ) 2.5 µV
Voltage Resistance Leakage = 40 µV/16
20 kΩ
1
Current
(I
OUT
)
2
+1 nA
–1 nA
Total error induced by a typical CMOS multiplexer
to an SPGA at +25°C 10.21 A
NOTES
1
The resistor for this calculation is the user-provided feedback resistance (R
F
).
20 kΩ is recommended value (see Resistor Programmable Gain Amplifier section).
2
The leakage currents (I
S
and I
OUT
) will induce an offset voltage, however, the offset
will be determined by the difference between the leakages of each “half’’ of the
differential multiplexer. The differential leakage current is multiplied by the
feedback resistance (see Note 1), to determine offset voltage. Because differential
leakage current is not a parameter specified on multiplexer data sheets, the most
extreme difference (one most positive and one most negative) was used for the
calculations in Table II. Typical performance will be much better.
**The frequency response and settling will be affected by the ON resistance and
internal capacitance of the multiplexer. Figure 40 shows the settling time vs.
ON resistance at different gain settings for an AD625 based SPGA.
**Switch resistance and leakage current errors can be reduced by using relays.
These capacitances may also be incorporated as part of the
external input protection circuit (see section on Input Protec-
tion). As a general practice every effort should be made to
match the extraneous capacitance at Pins 15 and 2, and Pins 1
and 16, to preserve high ac CMR.
SOFTWARE PROGRAMMABLE GAIN AMPLIFIER
An SPGA provides the ability to externally program precision
gains from digital inputs. Historically, the problem in systems
requiring electronic switching of gains has been the ON resis-
tance (R
ON
) of the multiplexer, which appears in series with the
gain setting resistor R
G
. This can result in substantial gain errors
and gain drifts. The AD625 eliminates this problem by making
the gain drive and gain sense pins available (Pins 2, 15, 5, 12;
see Figure 39). Consequently the multiplexer’s ON resistance is
removed from the signal current path. This transforms the ON
resistance error into a small nullable offset error. To clarify this
point, an error budget analysis has been performed in Table II
based on the SPGA configuration shown in Figure 39.
+GAIN
SENSE
+INPUT
–INPUT
RTI NULL
RTI NULL
+V
S
+GAIN DRIVE –GAIN DRIVE
NC
REF
–V
S
V
OUT
+V
S
A1 A2
AD625
10k
10k 10k
10k
A3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–GAIN
SENSE
TTL/DTL TO CMOS LEVEL TRANSLATOR
DECODER/DRIVER
3.9k 975 650 975 3.9k
15.6k 15.6k20k 20k
AD7502
A0
A1
E
N
V
SS
V
DD
GND
–V
S
RTO NULL
RTO NULL
Figure 38. SPGA in a Gain of 16
Figure 38 shows an AD625 based SPGA with possible gains of
1, 4, 16, 64. R
G
equals the resistance between the gain sense
lines (Pins 2 and 15) of the AD625. In Figure 38, R
G
equals
the sum of the two 975 Ω resistors and the 650 Ω resistor, or
2600 Ω. R
F
equals the resistance between the gain sense and the
gain drive pins (Pins 12 and 15, or Pins 2 and 5), that is R
F
equals the 15.6 kΩ resistor plus the 3.9 kΩ resistor, or 19.5 kΩ.
The gain, therefore equals:
2R
F
R
G
+1=
2(19.5kΩ)
(2.6 kΩ)
+1=16
As the switches of the differential multiplexer proceed synchro-
nously, R
G
and R
F
change, resulting in the various programmed
gain settings.
AD625
REV. D–14–
GAIN
1000
1
SETTLING TIME – s
800
400
200
100
80
40
20
10
8
4
2
1
4 16 64 256 1024 4096
R
ON
= 1k
R
ON
= 500
R
ON
= 200
R
ON
= 0
Figure 40. Time to 0.01% of a 20 V Step Input for
SPGA with AD625
DETERMINING SPGA RESISTOR NETWORK VALUES
The individual resistors in the gain network can be calculated
sequentially using the formula given below. The equation deter-
mines the resistors as labeled in Figure 41. The feedback resis-
tors and the gain setting resistors are interactive, therefore; the
formula must be a series where the present term is dependent on
the preceding term(s). The formula
RkR
G
G
G
R
F
i
F
j
j
i
i
F
+
=
=
=
=
=
∑
1
0
1
1
0
0
20 1
1
0
( – )( – )Ω
can be used to calculate the necessary feedback resistors for any
set of gains. This formula yields a network with a total resistance
of 40 kΩ. A dummy variable (j) serves as a counter to keep a
running total of the preceding feedback resistors. To illustrate
how the formula can be applied, an example similar to the
calculation used for the resistor network in Figure 38 is exam-
ined below.
1) Unity gain is treated as a separate case. It is implemented
with separate 20 kΩ feedback resistors as shown in Figure 41.
It is then ignored in further calculations.
2) Before making any calculations it is advised to draw a resistor
network similar to the network in Figure 41. The network
will have (2 × M) + 1 resistors, where M = number of gains.
For Figure 38 M = 3 (4, 16, 64), therefore, the resistor string
will have seven resistors (plus the two 20 kΩ “side” resistors
for unity gain).
3) Begin all calculations with G
0
= 1 and R
F
0
= 0.
R
F
1
= (20 kΩ – R
F
0
) (1–1/4): R
F
0
= 0 ∴ R
F
1
= 15 kΩ
R
F
2
= [20 kΩ – (R
F
0
+ R
F
1
)] (1–4/16):
R
F
0
+ R
F
1
= 15 kΩ ∴ R
F
2
= 3.75 kΩ
R
F
3
= [20 kΩ – (R
F
0
+ R
F
1
+ R
F
2
)] (1–16/64):
R
F
0
+ R
F
1
+ R
F
2
= 18.75 kΩ ∴ R
F
3
= 937.5 Ω
4) The center resistor (R
G
of the highest gain setting), is deter-
mined last. Its value is the remaining resistance of the 40 kΩ
string, and can be calculated with the equation:
Rk R
GF
j
j
M
=
=
∑
( – )40 2
0
Ω
R
G
= 40 k
Ω
– 2 (R
F
0
+ R
F
1
+ R
F
2
+
R
F
3
)
40 k
Ω
– 39.375 k
Ω
= 625
Ω
5) If different resistor values are desired, all the resistors in the
network can be scaled by some convenient factor. However,
raising the impedance will increase the RTO errors, lowering
the total network resistance below 20 kΩ can result in ampli-
fier instability. More information on this phenomenon is
given in the RPGA section of the data sheet. The scale factor
will not affect the unity gain feedback resistors. The resistor
network in Figure 38 has a scaling factor of 650/625 = 1.04,
if this factor is used on R
F
1
, R
F
2
, R
F
3
, and R
G
, then the resis-
tor values will match exactly.
6) Round off errors can be cumulative, therefore, it is advised to
carry as many significant digits as possible until all the values
have been calculated.
AD75xx
TO GAIN SENSE
(PIN 2)
20k RF
1
20k
RF
2
RF
N
RF
G
RF
N
RF
2
TO GAIN SENSE
(PIN 15)
TO GAIN DRIVE
(PIN 5)
TO GAIN DRIVE
(PIN 12)
CONNECT IF UNITY
GAIN IS DESIRED
CONNECT IF UNITY
GAIN IS DESIRED
Figure 41. Resistors for a Gain Setting Network
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

5962-8771901EA

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Analog Devices Inc.
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Instrumentation Amplifiers PROGRAMMABLE GAIN IN-AMP
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