12
LTC1291
1291fa
STAA $102A LOAD DUMMY DIN INTO SPI,
START SCK
WAIT3 LDAA $1029 CHECK SPI STATUS REG
BPL WAIT3 CHECK IF TRANSFER IS DONE
BSET $08,X#$01 D0 GOES HIGH (CS GOES HIGH)
LDAA $102A LOAD LTC1291 LSBs IN ACC
STAA $63 STORE LSBs IN $63
JMP LOOP START NEXT CONVERSION
Interfacing to the Parallel Port of the Intel 8051 Family
The Intel 8051 has been chosen to show the interface
between the LTC1291 and parallel port microprocessors.
Usually the signals CS, D
IN
and CLK are generated on three
port lines and the D
OUT
signal is read on a fourth port line.
LDAA $1029 CHECK SPI STATUS REG
WAIT1 BPL WAIT1 CHECK IF TRANSFER IS DONE
LDAA $51 LOAD DIN INTO ACC A FROM $51
STAA $102A LOAD DIN INTO SPI, START SCK
WAIT2 LDAA $1029 CHECK SPI STATUS REG
BPL WAIT2 CHECK IF TRANSFER IS DONE
LDAA $102A LOAD LTC1291 MSBs INTO ACC A
STAA $62 STORE MSBs IN $62
LDAA $52 LOAD DUMMY DIN INTO ACC A
FROM $52
LABEL MNEMONIC OPERAND COMMENTS
LABEL MNEMONIC OPERAND COMMENTS
Timing Diagram for Interface to Intel 8051
Hardware and Software Interface to Intel 8051
LTC1291 AI09
D
OUT
FROM LTC1291 STORED IN 8051 RAM
00
0
0
B0
B2
B3 B1
B10
B11
LSB
MSB
R2
R1
B9
B8 B7
B6
B5 B4
CLK
D
OUT
CS
ANALOG
INPUTS
P1.4
P1.3
8051
D
IN
P1.2
MUX ADDRESS
A/D RESULT
LTC1291
CH0
CH1
This works very well. One can save a line by tying the D
IN
and D
OUT
lines together. The 8051 first sends the start bit
and MUX Address to the LTC1291 over the line connected
to P1.2. Then P1.2 is reconfigured as an input and the 8051
reads back the 12-bit A/D result over the same data line.
CS
CLK
DATA
(D
IN
/D
OUT
)
LTC1291 AI08
13
24
5
PS BIT LATCHED
INTO LTC1291
8051 P1.2 OUTPUT DATA
TO LTC1291
8051 P1.2 RECONFIGURED
AS INPUT AFTER THE 5TH RISING
CLK BEFORE THE 5TH FALLING CLK
LTC1291 SENDS A/D RESULT
BACK TO 8051 P1.2
LTC1291 TAKES CONTROL OF DATA
LINE ON 5TH FALLING CLK
START
B11
SGL/
DIFF
ODD/
SIGN
MSBF
PS
B10
B9
B8
B7
B6
B5
B4
B3 B2
B1
B0
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
