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LTC1291DCN8#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
4
LTC1291
1291fa
Supply Current vs Supply Voltage
Supply Current vs Temperature
CCHARA TERIST
ICS
UW
AT
Y
P
I
CA
LPER
F
O
R
C
E
Change in Gain vs Temperature
Change in Offset vs Supply
Voltage
SUPPLY VOLTAGE (V)
4
SUPPLY CURRENT (mA)
4
6
6
1291 G01
2
0
5
10
8
CLK = 1MHz
T
A
= 25°C
AMBIENT TEMPERATURE (°C)
–50
SUPPLY CURRENT (mA)
7
8
9
30 70
1291 G02
6
5
–30 –10
50 90
110
4
3
10
10
130
CLK = 1MHz
V
CC
= 5V
Change in Linearity vs Supply
Voltage
Change in Gain Error vs Supply
Voltage Change in Offset vs Temperature
Change in Linearity vs
Temperature
AMBIENT TEMPERATURE (°C)
–50
0
MAGNITUDE OF LINEARITY CHANGE (LSB)
0.2
0.5
0
50
75
1291 G07
0.1
0.4
0.3
–25
25
100
125
V
CC
= 5V
CLK = 1MHz
AMBIENT TEMPERATURE (°C)
–50
0
MAGNITUDE OF GAIN CHANGE (LSB)
0.2
0.5
0
50
75
1291 G08
0.1
0.4
0.3
–25
25
100
125
V
CC
= 5V
CLK = 1MHz
Minimum Clock Rate for
0.1 LSB Error
AMBIENT TEMPERATURE (°C)
–50
MINIMUM CLK FREQUENCY* (MHz)
0.15
0.20
0.25
50
1291 G09
0.10
0.05
–25
0
25
75
125100
V
CC
= 5V
* AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS THE
FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 1MHz VALUE IS FIRST DETECTED
SUPPLY VOLTAGE (V)
4.0
CHANGE IN LINEARITY (LSB = 1/4096 • V
CC
(V
REF
))
0.1
0.3
0.4
6.0
1291 G04
4.5
5.0
5.5
0.2
0.5
0
SUPPLY VOLTAGE (V)
4.0
CHANGE IN GAIN ERROR (LSB = 1/4096 × V
CC
(V
REF
))
0.1
0.3
0.4
6.0
1291 G05
–0.1
–0.3
–0.5
4.5
5.0
5.5
0.2
0.5
0
–0.2
–0.4
SUPPLY VOLTAGE (V)
4.0
CHANGE IN OFFSET (LSB = 1/4096 • V
CC
(V
REF
))
0.1
0.3
0.4
6.0
1291 G03
–0.1
–0.3
–0.5
4.5
5.0
5.5
0.2
0.5
0
–0.2
–0.4
AMBIENT TEMPERATURE (°C)
–50
0
MAGNITUDE OF OFFSET CHANGE (LSB)
0.2
0.5
0
50
75
1291 G06
0.1
0.4
0.3
–25
25
100
125
V
CC
= 5V
CLK = 1MHz
5
LTC1291
1291fa
CCHARA TERIST
ICS
UW
AT
Y
P
I
CA
LPER
F
O
R
C
E
D
OUT
Delay Time vs Temperature
Maximum Clock Rate vs Source
Resistance
Maximum Filter Resistor vs
Cycle Time
CYCLE TIME (µs)
10
MAXIMUM R
FILTER
** (Ω)
100
1k
10k
10
1k
10k
1291 G12
1
100
+
–
+V
IN
C
FILTER
≥1µF
R
FILTER
100
0.2
MAXIMUM CLK FREQUENCY* (MHz)
0.4
0.6
0.8
1.0
1k 10k 100k
1291 G11
0
V
CC
= 5V
CLK = 1MHz
R
SOURCE
–
(Ω)
+
–
+IN
–IN
+V
IN
R
SOURCE
–
AMBIENT TEMPERATURE (°C)
–50
0
INPUT CHANNEL LEAKAGE CURRENT (nA)
100
300
400
500
1000
700
–10
30
50 130
1291 G14
200
800
900
600
–30 10
70 90
110
ON CHANNEL
OFF CHANNEL
GUARANTEED
Input Channel Leakage Current
vs Temperature
Sample-and-Hold Acquisition
Time vs Source Resistance
* MAXIMUM CLK FREQUENCY REPRESENTS THE CLK
FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE
ERROR AT ANY CODE TRANSITION FROM ITS 1MHz
VALUE IS FIRST DETECTED
**MAXIMUM R
FILTER
REPRESENTS THE FILTER RESISTOR
VALUE AT WHICH A 0.1LSB CHANGE IN FULL SCALE
ERROR FROM ITS VALUE AT R
FILTER
= 0Ω IS FIRST
DETECTED
PI FU CTIO S
U
UU
AMBIENT TEMPERATURE (°C)
–50
D
OUT
DELAY TIME FROM CLK↓ (ns)
150
200
250
50
1291 G10
100
0
–25
0
25
75
125100
V
CC
= 5V
50
MSB-FIRST DATA
LSB-FIRST DATA
R
SOURCE
+ (Ω)
100
1
S/H AQUISITION TIME TO 0.02% (µs)
10
100
1k 10k
1291 G13
+
–
V
IN
R
SOURCE
+
V
CC
= 5V
T
A
= 25°C
0V TO 5V INPUT STEP
CS (Pin 1): Chip Select Input. A logic low on this input
enables the LTC1291.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
D
IN
(Pin 5): Digital Data Input. The multiplexer address is
shifted into this input.
D
OUT
(Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the serial
data transfer.
V
CC
(V
REF
) (Pin 8): Positive Supply and Reference Voltage.
This pin provides power and defines the span of the A/D
converter. This supply must be kept free of noise and
ripple by bypassing directly to the analog ground plane.
6
LTC1291
1291fa
W
IDAGRA
B
L
O
C
K
TEST CIRCUITS
Load Circuit for t
dDO
, t
r
and t
f
Load Circuit for t
dis
and t
en
On and Off Channel Leakage Current
5V
A
A
I
OFF
I
ON
POLARITY
OFF CHANNEL
ON CHANNEL
1291 TC01
Voltage Waveforms for t
dis
D
OUT
3k
100pF
TEST POINT
5V t
dis
WAVEFORM 2, t
en
t
dis
WAVEFORM 1
1291 TC05
D
OUT
WAVEFORM 1
(SEE NOTE 1)
2.0V
t
dis
90%
10%
D
OUT
WAVEFORM 2
(SEE NOTE 2)
CS
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
1291 TC06
INPUT
SHIFT
REGISTER
COMP
SAMPLE
AND
HOLD
12-BIT
CAPACITIVE
DAC
OUTPUT
SHIFT
REGISTER
12-BIT
SAR
CONTROL
AND
TIMING
V
CC
(V
REF
)
8
ANALOG
INPUT MUX
2
3
GND
4
CH1
CH0
D
OUT
6
1
CLK
7
CS
1291 BD
5
D
IN
D
OUT
1.4V
3k
100pF
TEST POINT
1291 TC02
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LTC1291DCN8#PBF

Mfr. #:
Buy LTC1291DCN8#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-Bit Serial I/O 2/Ch Input ADC
Lifecycle:
New from this manufacturer.
Delivery:
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