P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 24 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
in reset when V
DD
falls below the minimum specified operating voltage. These
requirements for clock frequencies above 12 MHz do not apply when using the
internal RC oscillator in clock doubler mode.
7.3.6 Clock output
The P89LPC952/954 supports a user-selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if
another clock source has been selected (on-chip RC oscillator, watchdog oscillator,
external clock input on XTAL1) and if the RTC is not using the crystal oscillator as its clock
source. This allows external devices to synchronize to the P89LPC952/954. This output is
enabled by the ENCLK bit in the TRIM register.
The frequency of this clock output is
1
⁄
2
that of the CCLK. If the clock output is not needed
in Idle mode, it may be turned off prior to entering Idle, saving additional power.
7.4 On-chip RC oscillator option
The P89LPC952/954 has a 6-bit TRIM register that can be used to tune the frequency of
the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed
value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature.
End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to
other frequencies. When the clock doubler option is enabled (UCFG1.3 = 1), the output
frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can
be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing
highest performance access. This bit can then be set in software if CCLK is running at
8 MHz or slower.
The requirements in Section 7.3.5 “High speed oscillator option” for configuring P1.5 as
an external reset input and using an external reset circuit when the clock frequency is
greater than 12 MHz do not apply when using the internal RC oscillator’s clock doubler
option.
7.5 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator
can be used to save power when a high clock frequency is not needed.
7.6 External clock input option
In this configuration, the processor clock is derived from an external source driving the
P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be
used as a standard port pin or a clock output.
When using an external clock input frequency above 12 MHz, the reset input
function of P1.5 must be enabled. An external circuit is required to hold the device
in reset at power-up until V
DD
has reached its specified level. When system power is
removed V
DD
will fall below the minimum specified operating voltage. When using
an external clock input frequency above 12 MHz, in some applications, an external
brownout detect circuit may be required to hold the device in reset when V
DD
falls
below the minimum specified operating voltage. These requirements for clock
frequencies above 12 MHz do not apply when using the internal RC oscillator in
clock doubler mode.
