LTC3534
7
3534fb
For more information www.linear.com/LTC3534
GND Pads (Pins 1, 8, 9, 16; GN Package): IC Substrate
Grounds. These pins MUST be soldered to the printed
circuit board ground to provide both electrical contact
and a good thermal contact to the PCB.
RUN/SS (Pin 2): Combined Shutdown and Soft-Start. Ap
-
plying a voltage below 400mV shuts down the IC. Apply
a voltage above 1.4V to enable the IC and above 2.4V to
ensure that the error amp is not clamped from soft-start.
An R-C from the enable command signal to this pin will
provide a soft-start function by limiting the rise time of
the V
C
pin. PWM mode operation must be commanded
to properly enable the IC.
GND (Pin 3): Signal Ground for the IC.
PGND1, PGND2 (Pins 4, 7): Power Ground for the Internal
N-channel MOSFET Power Switches (Switches B and C).
SW1 (Pin 5): Switch Pin where Internal Switches A and
B are Connected. Connect inductor from SW1 to SW2.
Minimize trace length to reduce EMI.
SW2 (Pin 6): Switch Pin where Internal Switches C and
D are Connected. Minimize trace length to reduce EMI.
PWM (Pin 10): Burst Mode Select. PWM must be driven
HIGH during start-up. When V
OUT
is in regulation, the
PWM pin may be driven LOW to command Burst Mode
operation. Applying a voltage below 400mV enables Burst
Mode operation, providing a significant efficiency improve
-
ment at light loads. Burst Mode operation will continue
until this pin is driven high. Applying a voltage above 1.4V
disables Burst Mode operation, enabling low noise, fixed
frequency operation.
V
OUT
(Pin 11): Output of the Synchronous Rectifier. A filter
capacitor is placed from V
OUT
to GND. A ceramic bypass
capacitor is recommended as close to the V
OUT
and GND
pins as possible. V
OUT
is given by the following equation:
V
OUT
= 1.000
R1+R2
R2
V
PV
IN
(Pin 12): Power V
IN
Supply Pin. A 10µF ceramic
capacitor is recommended as close to the PV
IN
and PGND
pins as possible.
V
IN
(Pin 13): Input Supply Pin. Connect the power source
to this pin.
V
C
(Pin 14): Error Amp Output. An R-C network is con-
nected from this pin to FB for loop compensation. Refer
toClosing the Feedback Loop” section for component
selection guidelines.
FB (Pin 15): Feedback Pin. Connect V
OUT
resistor divider
tap to this pin. The output voltage can be adjusted from
1.8V to 7V. The feedback reference voltage is typically 1V.
Exposed Pad (Pin 17; DHC Package): IC Substrate Ground.
This pin MUST be soldered to the printed circuit board
ground to provide both electrical contact and a good
thermal contact to the PCB.
pin FuncTions
LTC3534
8
3534fb
For more information www.linear.com/LTC3534
block DiagraM
+
+
+
+
+
PWM
LOGIC
AND
OUTPUT
PHASING
GATE
DRIVERS
AND
ANTICROSS
CONDUCTION
Burst Mode OPERATION
CONTROL
UVLO
2.2V
SUPPLY
CURRENT
LIMIT
SW A
SW1
PV
IN
V
IN
RUN/SS
R
SS
C
SS
SW2
L1
ANTIRING
V
IN
2.4V TO 7V
SW D
REVERSE
CURRENT
LIMIT
AVERAGE
CURRENT
LIMIT
SW B
1.8A
SW C
PGND2PGND1
–500mA
+
+
+
+
PGND2PGND1 GND EXPOSED PAD
V
OUT
11
15
14
71734
2
10
65
12
13
FB
V
C
C
P1
R
Z
C
P2
PWM
SLEEP
3534 BD
V
OUT
1.8V TO 7V
PWM
COMPARATORS
+
1
100k
G
m
=
2.6A
+
THERMAL
SHUTDOWN
SHUTDOWN
AND
SOFT-START
1MHz
OSC
V
REF
1V
ERROR
AMP
C
IN
SHUTDOWN
C
OUT
C
Z1
R
FF
R1
R2
LTC3534
9
3534fb
For more information www.linear.com/LTC3534
operaTion
The LTC3534 provides high efficiency, low noise power
for a wide variety of handheld electronic devices. Linear
Technology’s proprietary topology allows input voltages
above, below or equal to the output voltage by properly
phasing the output switches. The error amplifier output
voltage on V
C
determines the output duty cycle of the
switches. Since V
C
is a filtered signal, it provides rejection
of frequencies from well below the switching frequency.
The low R
DS(ON)
, low gate charge synchronous switches
provide high frequency pulse width modulation control at
high efficiency. High efficiency is achieved at light loads
when Burst Mode operation is invoked and the LTC3534’s
quiescent current drops to a mere 25µA.
LOW NOISE FIXED FREQUENCY OPERATION
Oscillator
The frequency of operation is internally set to 1MHz.
Error Amplifier
The error amplifier is a voltage mode amplifier. The loop
compensation components are configured around the
amplifier (from FB to V
C
) to obtain stability of the converter.
For improved bandwidth, an additional R-C feedforward
network can be placed across the upper feedback divider
resistor. The voltage on RUN/SS clamps the error amplifier
output, V
C
, to provide a soft-start function.
Supply Current Limits
There are
two different supply current limit circuits in the
LTC3534, each having internally fixed thresholds.
The first circuit is an average current limit amplifier, sourc
-
ing current out of FB to drop the output voltage should
the peak input current exceed 1.8A typical. This method
provides a closed loop means of clamping the input cur
-
rent. During conditions where V
OUT
is near ground, such
as during a short circuit or start-up, this threshold is cut
to 800mA typical, providing a foldback feature. For this
current limit feature to be most effective, the Thevenin
resistance from FB to ground should be greater than 100k.
Should the peak input current exceed 2.6A typical, the
second circuit, a high speed peak current limit compara
-
tor, shuts off PMOS switch A. The delay to output of this
comparator is typically 50ns.
Reverse Current Limit
During fixed frequency operation, the LTC3534 operates
in forced continuous conduction mode. The reverse cur
-
rent limit comparator monitors the inductor current from
the output through PMOS switch D. Should this negative
inductor current exceed 500mA typical, the LTC3534
shuts off switch D.
Four-Switch Control
Figure 1 shows a simplified diagram of how the four internal
switches are connected
to the inductor, PV
IN
, V
OUT
, PGND1
and PGND2. Figure 2 shows the regions of operation for
the LTC3534 as a function of the internal control voltage,
V
CI
. Dependent on the magnitude of V
CI
, the LTC3534 will
operate in buck, buck-boost or boost mode. V
CI
is a level
5
SW1
6
SW2L1
PMOS A
NMOS B
12
PV
IN
PMOS D
NMOS C
3534 F01
11
4 7
V
OUT
PGND1 PGND2
85%
D
MAX
BOOST
D
MIN
BOOST
D
MAX
BUCK
DUTY
CYCLE
0%
V4 (1.2V)
INTERNAL
CONTROL
VOLTAGE, V
CI
V3 (720mV)
BOOST REGION
BUCK REGION
BUCK-BOOST REGION
V2 (640mV)
V1 (100mV)
3534 F02
A ON, B OFF
PWM C AND D
SWITCHES
D ON, C OFF
PWM A AND B
SWITCHES
FOUR SWITCH PWM
Figure 1. Simplified Diagram of Output Switches Figure 2. Switch Control vs Internal Control Voltage, V
CI

LTC3534EGN#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 7V, 500mA Sync Buck-Boost DC/DC Conv
Lifecycle:
New from this manufacturer.
Delivery:
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