4
AT24C1024
1471I–SEEPR–7/03
Pin Capacitance
(1)
Note: 1. This parameter is characterized and is not 100% tested.
DC Characteristics
Note: 1. V
IL
min and V
IH
max are reference only and are not tested.
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +2.7V.
Symbol Test Condition Max Units Conditions
C
I/O
Input/Output Capacitance (SDA) 8 pF V
I/O
= 0V
C
IN
Input Capacitance (A
1
, SCL) 6 pF V
IN
= 0V
Applicable over recommended operating range from: T
AI
= -40°C to +85°C, V
CC
= +2.7V to +5.5V, T
AC
= 0°C to +70°C,
V
CC
= +2.7V to +5.5V (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
V
CC
Supply Voltage 2.7 5.5 V
I
CC
Supply Current V
CC
= 5.0V READ at 400 kHz 2.0 mA
I
CC
Supply Current V
CC
= 5.0V WRITE at 400 kHz 5.0 mA
I
SB
Standby Current
V
CC
= 2.7V V
IN
= V
CC
or V
SS
3.0 µA
V
CC
= 5.5V 6.0 µA
I
LI
Input Leakage Current V
IN
= V
CC
or
V
SS
0.10 3.0 µA
I
LO
Output Leakage
Current
V
OUT
= V
CC
or
V
SS
0.05 3.0 µA
V
IL
Input Low Level
(1)
-0.6 V
CC
x 0.3 V
V
IH
Input High Level
(1)
V
CC
x 0.7 V
CC
+ 0.5 V
V
OL
Output Low Level V
CC
= 3.0V I
OL
= 2.1 mA 0.4 V
5
AT24C1024
1471I–SEEPR–7/03
AC Characteristics
Notes: 1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
R
L
(connects to V
CC
): 1.3 k (2.7V, 5V)
Input pulse voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times: 50 ns
Input and output timing reference voltages: 0.5 V
CC
Applicable over recommended operating range from T
A
= -40°C to +85°C, V
CC
= +2.7V to +5.5V, C
L
= 100 pF (unless
otherwise noted). Test conditions are listed in Note 2.
Symbol Parameter Test Conditions Min Max Units
f
SCL
Clock Frequency, SCL
4.5V V
CC
5.5V
2.7V V
CC
5.5V
1000
400
kHz
t
LOW
Clock Pulse Width Low
4.5V V
CC
5.5V
2.7V V
CC
5.5V
0.4
1.3
µs
t
HIGH
Clock Pulse Width High
4.5V V
CC
5.5V
2.7V V
CC
5.5V
0.4
0.6
µs
t
AA
Clock Low to Data Out Valid
4.5V V
CC
5.5V
2.7V V
CC
5.5V
0.05
0.05
0.55
0.9
µs
t
BUF
Time the bus must be free before a new
transmission can start
(1)
4.5V V
CC
5.5V
2.7V V
CC
5.5V
0.5
1.3
µs
t
HD.STA
Start Hold Time
4.5V V
CC
5.5V
2.7V V
CC
5.5V
0.25
0.6
µs
t
SU.STA
Start Setup Time
4.5V V
CC
5.5V
2.7V V
CC
5.5V
0.25
0.6
µs
t
HD.DAT
Data In Hold Time 0 µs
t
SU.DAT
Data In Setup Time 100 ns
t
R
Inputs Rise Time
(1)
0.3 µs
t
F
Inputs Fall Time
(1)
4.5V V
CC
5.5V
2.7V V
CC
5.5V
100
300
ns
t
SU.STO
Stop Setup Time
4.5V V
CC
5.5V
2.7V V
CC
5.5V
0.25
0.6
µs
t
DH
Data Out Hold Time 50 ns
t
WR
Write Cycle Time 10 ms
Endurance
(1)
5.0V, 25°C, Page Mode 100K Write Cycles
6
AT24C1024
1471I–SEEPR–7/03
Device
Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (refer to Data
Validity timing diagram). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (refer to Start and Stop Definition timing diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the Stop command will place the EEPROM in a standby power mode (refer to
Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-
edge that it has received each word.
STANDBY MODE: The AT24C1024 features a low-power standby mode which is enabled: a)
upon power-up and b) after the receipt of the STOP bit and the completion of any internal
operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be reset by following these steps:
1. Clock up to 9 cycles,
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.

AT24C1024-10CI-2.7

Mfr. #:
Manufacturer:
Description:
IC EEPROM 1M I2C 1MHZ 8LAP
Lifecycle:
New from this manufacturer.
Delivery:
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