LTC2605/LTC2615/LTC2625
13
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OPERATION
The format of the three data bytes is shown in Figure 2.
The fi rst byte of the input word consists of the 4-bit com-
mand and 4-bit DAC address. The next two bytes consist
of the 16-bit data word. The 16-bit data word consists of
the 16-, 14- or 12-bit input code, MSB to LSB, followed by
0, 2 or 4 don’t care bits (LTC2605, LTC2615 and LTC2625
respectively). A typical I
2
C write transaction is shown in
Figure 3.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The fi rst four commands in the table
consist of write and update operations. A write operation
loads the 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than eight outputs are needed. When in power down, the
buffer amplifi ers and reference inputs are disabled and
draw essentially zero current. The DAC outputs are put into
a high impedance state, and the output pins are passively
pulled to ground through individual 90k resistors. When
all eight DACs are powered down, the bias generation
circuit is also disabled. Input and DAC registers are not
disturbed during power down.
Any channel or combination of channels can be put into
power-down mode by using command 0100
b
in combi-
nation with the appropriate DAC address, (n). The 16-bit
data word is ignored. The supply and reference currents
are reduced by approximately 1/8 for each DAC powered
down; the effective resistance at REF (Pin 6) rises accord-
ingly, becoming a high impedance input (typically >1GΩ)
when all eight DACs are powered down.
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 1.
The selected DAC is powered up as its voltage output is
updated.
There is an initial delay as the DAC powers up before it
begins its usual settling behavior. If less than eight DACs
are in a powered-down state prior to the updated com-
mand, the power-up delay is 5μs. If, on the other hand,
all eight DACs are powered down, then the bias genera-
tion circuit is also disabled and must be restarted. In this
case, the power-up delay is greater: 12μs for V
CC
= 5V,
30μs for V
CC
= 3V.
S
INPUT WORD
WRITE WORD PROTOCOL FOR LTC2605/LTC2615/LTC2625
INPUT WORD (LTC2605)
SLAVE ADDRESS
W
A
A1ST DATA BYTE
2ND DATA BYTE A
3RD DATA BYTE
AP
2605 F02
1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE
1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE
1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE
C3
C2
C1
C0
A3
A2
A1
A0
D13D14D15
D12
D11 D10 D9 D8
D7
D6
D5 D4 D3 D2 D1
D0
INPUT WORD (LTC2615)
C3
C2
C1
C0
A3
A2
A1
A0
D11D12D13
D10
D9 D8 D7 D6
D5
D4
D3 D2 D1 D0 X
X
INPUT WORD (LTC2625)
C3
C2
C1
C0
A3
A2
A1
A0
D9D10D11
D8
D7 D6 D5 D4
D3
D2
D1 D0 X X X
X
Figure 2
LTC2605/LTC2615/LTC2625
14
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OPERATION
ACK ACK
123456789123456789123456789123456789
2605 F03
ACK
START STOP
FULL-SCALE
VOLTAGE
ZERO-SCALE
VOLTAGE
SDA
SA6 SA5 SA4 SA3 SA2 SA1 SA0
SCL
V
OUT
C2C3
C3 C2 C1 C0 A3 A2 A1 A0
C1 C0 A3 A2 A1 A0
ACK
COMMAND
D15 D14 D13 D12 D11 D10 D9 D8
MS DATA
D7 D6 D5 D4 D3 D2 D1 D0
LS DATA
SA6 SA5 SA4 SA3 SA2 SA1 SA0 WR
SLAVE ADDRESS
Figure 3. Typical LTC2605 Input Waveform—Programming DAC Output for Full-Scale
LTC2605/LTC2615/LTC2625
15
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Voltage Outputs
Each of the eight rail-to-rail amplifi ers contained in these
parts has guaranteed load regulation when sourcing or
sinking up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplifi ers ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed
in LSB/mA.
DC output impedance is equivalent to load regulation and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifi ers DC output
impedance is 0.020Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30Ω • 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The amplifi ers are stable driving capacitive loads of up
to 1000pF.
Board Layout
The excellent load regulation and DC-crosstalk performance
of these devices is achieved in part by keeping “signal”
and “power” grounds separated internally and by reducing
shared internal resistance to just 0.005Ω.
The GND pin functions both as the node to which the refer-
ence and output voltages are referred and as a return path
for power currents in the device. Because of this, careful
thought should be given to the grounding scheme and
board layout in order to ensure rated performance.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the
use of separate digital and analog ground planes which
have minimal capacitive and resistive interaction with
each other.
OPERATION
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. Resistance here will
add directly to the effective DC output impedance of the
device (typically 0.020Ω), and will degrade DC crosstalk.
Note that the LTC2605/LTC2615/LTC2625 are no more
susceptible to these effects than other parts of their type;
on the contrary, they allow layout-based performance
improvements to shine rather than limiting attainable
performance with excessive internal resistance.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown
in Figure 4b. Similarly, limiting can occur near full-scale
when the REF pin is tied to V
CC
. If V
REF
= V
CC
and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at V
CC
as shown in Figure 4c. No full-scale
limiting can occur if V
REF
is less than V
CC
– FSE.
Offset and linearity are defi ned and tested over the region
of the DAC transfer function where no output limiting
can occur.

LTC2625IGN-1#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Octal 12-bit I2C Voltage Output DAC
Lifecycle:
New from this manufacturer.
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