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POWER MANAGEMENT
SC2595
Layout guidelinesLayout guidelines
Layout guidelinesLayout guidelines
Layout guidelines
1)The SC2595 has a SOIC8-EDP package. It can improve
the thermal impedance (
θ
JC
) significantly. A suitable ther-
mal pad should be added when PCB layout. Some ther-
mal vias are required to connect the thermal pad to the
PCB ground layer. This will improve the thermal perfor-
mance .
2)To increase the noise immunity, a ceramic capacitor of
10nf to 100nf is required to decouple the V
REF
pin with
the shortest connection trace, also A 10nF to 100nF
ceramic capacitor close to the V
SENSE
pin is required to
avoid oscillation during transient condition.
3)To reduce the noise on the input power rail for stan-
dard SSTL-2 application, a 68μF low ESR capacitor and
a 1μF ceramic capacitor have to be used on the input
power rail with shortest possible connection.
4)For lower power loss SSTL-2 application, a 220μF AL.
capacitor (ESR should be lower than 250m ohm) and a
10μF ceramic has to be added on the PV
CC
pin and a 1μF
ceramic capacitor +5.1 ohm filter has to be added on
the V
DDQ
pin with shortest possible connection.
5)V
TT
output copper plane should be as large as possible.
6)V
SENSE
trace should be as short as possible.
Application Information (Cont.)
