I
DD
Specifications
Table 9: DDR2 I
CDD
Specifications and Conditions – 4GB (Die Revision G)
Values shown for MT47H512M4 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (512 Meg x
4) component data sheet
Parameter
Combined
Symbol
-80E/
-800 -667 Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC
(I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
I
CDD0
1836 1746 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL = 4,
CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data pattern is same as I
DD4W
I
CDD1
2196 2016 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
I
CDD2P
252 252 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
I
CDD2Q
1026 846 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
I
CDD2N
1116 936 mA
Active power-down current: All device banks open;
t
CK =
t
CK (I
DD
); CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
CDD3P
846 666 mA
Slow PDN exit
MR[12] = 1
306 306
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS
MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are switch-
ing
I
CDD3N
1296 1206 mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
I
CDD4W
2826 2376 mA
Operating burst read current: All device banks open; Continuous burst read,
I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
I
CDD4R
2826 2376 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
I
CDD5
4446 4086 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
I
CDD6
252 252 mA
4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM VLP RDIMM
I
DD
Specifications
PDF: 09005aef83c60a84
hvs36c512_1gx72pz.pdf - Rev. E 4/14 EN
10
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