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9LP525BF-2LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
IDT
TM
/ICS
TM
PC MAIN CLOCK 1397—11/08/10
ICS9LP525-2
PC MAIN CLOCK
10
FS
L
C
2
B0b7
FS
L
B
1
B0b6
FS
L
A
1
B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
0 0 0 266.66
0 0 1 133.33
0 1 0 200.00
0 1 1 166.66
1 0 0 333.33
1 0 1 100.00
1 1 0 400.00
1 1 1
1. FS
L
A and FS
L
B are low-threshold inputs.Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
L
C is a three-level input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Table 1: CPU Frequency Select Table
Reserved
100.00 33.33 14.318 48.00 96.00
Pin 17 Pin 18
Spread
MHz MHz %
0 0 0 0
0 0 0 1 100.00 100.00 0.5% Down Spread SRC clocks from SRC_MAIN
0 0 1 0 100.00 100.00 0.5% Down Spread Only SRCCLK1 from PLL3
0 0 1 1 100.00 100.00 1% Down Spread Only SRCCLK1 from PLL3
0 1 0 0 100.00 100.00 1.5% Down Spread Only SRCCLK1 from PLL3
0 1 0 1 100.00 100.00 2% Down Spread Only SRCCLK1 from PLL3
0 1 1 0 100.00 100.00 2.5% Down Spread Only SRCCLK1 from PLL3
0 1 1 1
N/A N/A N/A N/A
1 0 0 0 24.576 24.576 None 24.576Mhz on SE1 and SE2
1 0 0 1 24.576 98.304 None 24.576Mhz on SE1, 98.304Mhz on SE2
1 0 1 0 98.304 98.304 None 98.304Mhz on SE1 and SE2
1 0 1 1 27.000 27.000 None 27Mhz on SE1 and SE2
1 1 0 0 25.000 25.000 None 25Mhz on SE1 and SE2
1 1 0 1
N/A N/A N/A N/A
1 1 1 0
N/A N/A N/A N/A
1 1 1 1
N/A N/A N/A N/A
B1b1B1b4 B1b3 B1b2
Table 2: PLL3 Quick Configuration (only applies in Mode 0, see Table 6)
Comment
PLL 3 disabled
Table 3: IO_Vout select table
B9b2
B9b1
B9b0
IO_Vout
0 0 0 0.3V
0 0 1 0.4V
0 1 0 0.5V
0 1 1 0.6V
1 0 0 0.7V
1 0 1 0.8V
1 1 0 0.9V
1 1 1 1.0V
IDT
TM
/ICS
TM
PC MAIN CLOCK 1397—11/08/10
ICS9LP525-2
PC MAIN CLOCK
11
Table 4: Device ID table
0 0 0 0
B8b7 B8b6 B8b5 B8b4 Comment
56 pin TSSOP
Table 5: Slew Rate Selection Table
Bit 1 Bit 0
0 0
0 1
1 0
1 1 1X (2.0 V/ns)
Slew Rate
HI-Z
0.7X (1.4V/ns)
0.8X (1.6 V/ns)
Table 6. PCI3 Configuration Table
PCI3_CFG1
(Byte 11, bit 7)
PCI3_CFG0
(Byte 11, bit 6)
Low 0 or 1 0 0 0 0 = Default
Mid 0 or 1 0 1 1 1
High TME=0 1 0 1 2
High TME=1 1 1 1 3
Table 7. PLL Modes for PCI3 Configurations
Outputs SSC Outputs SSC Outputs SSC
0 = Default
CPU/SRC/
PCI Down USB NA - - 100MHz
PLL1
(Table 2
applies)
1 CPU Down USB NA SRC/PCI Down 100MHz PLL3
2 CPU Center USB NA SRC/PCI Down 100MHz PLL3
3 CPU Center USB/LAN25 NA SRC/PCI Down 25MHz SE PLL2*
*Note: In Mode 3, Byte 8, bit (1:0) must be set to '1' to enable pin 17,18
Table 8. ME Clock Selection Table
PCIF5/
ITP_EN
iAMT_EN CPU2_AMT_EN CPU1_AMT_EN
x 1 0 0
x 1 0 1
1 1 1 0
1 1 1 1
PCI3/CFG0
HW Strap
PCI2/TME
HW Strap Config Mode
Note: 2 bits are needed since
CFG0 is tri-level input
Config
Mode
PLL1 PLL2 PLL3
CPU2 = iAMT Clock
CPU1 and CPU2 both run in iAMT mode
Reserved
Description
SRC_Main_SE
L
(Byte 0, bit 2)
SRC1
PLL Source
Default, CPU1 = iAMT Clock
IDT
TM
/ICS
TM
PC MAIN CLOCK 1397—11/08/10
ICS9LP525-2
PC MAIN CLOCK
12
PCI_STOP# Power Management
SMBus OE Bit PCI_STOP# Stoppable Free running Stoppable Free running
1
Running Running Running Running
CK= High
CK# = Low
Running
CK= Pull down
CK# = Low
Running
Disable
X
CPU_STOP# Power Management
SMBus OE Bit
PCI_STOP#
Stoppable
Free running
1
Running Running
CK= High
CK# = Low
Running
CK= Pull down
CK# = Low
Running
Disable
X
CR# Power Management
SMBus OE Bit
CR#
Stoppable
Free running
1
Running Running
0
Disable
X
PD# Power Management
Device State
w/o Latched input
w/Latched input
Latches Open
Power Down
M1
Virtual Power Cycle
to Latches Open
CPU1
CK= Pull down, CK# = Low
CK= Pull down, CK# = Low CK= Pull down, CK# = Low
Running
Differential Clocks
(Except CPU1)
CK= Pull down
CK# = Low
Enable
CK= Pull down, CK# = Low
CK= Pull down, CK# = Low
Low Hi-Z
Single-ended Clocks
CK= Pull down
CK# = Low
CK= Pull down
CK# = Low
Enable
0
CK= Pull down, CK# = Low
Low
Enable
0
Low Low
Single-ended Clocks
Differential Clocks
(Except CPU)
Low
CK = Pull down, CK# = Low
Differential Clocks
Differential Clocks
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

9LP525BF-2LF

Mfr. #:
Buy 9LP525BF-2LF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CK505 PCIe Gen2
Lifecycle:
New from this manufacturer.
Delivery:
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