LTC6410-6
11
64106fa
APPLICATIONS INFORMATION
Introduction
The LTC6410-6 is a low noise differential high speed
amplifi er. By default, the LTC6410-6 has 6dB voltage gain
and is designed to operate with 50 differential input and
output impedances. By changing (R
EXT
), alternative con-
fi gurations provide input resistances of up to 400, with
correspondingly lower noise fi gure and higher power gain.
The Block Diagram shows the basic circuit along with key
external components while Table 1 provides confi guration
information. If the input is AC-coupled, the V
BIAS
pin sets
the input common mode voltage and therefore the output
common mode voltage.
Input Impedance
LTC6410-6 has been designed with very fl exible input
termination circuitry. By default, with the termination pins
connected directly to the inputs, the input impedance is
58, see the Block Diagram. Internally, there is 110
between each input and the opposite output (R
T
). Divid-
ing the resistor by the internal noise gain of 2.7 + 1 = 3.7,
29.5 input impedance is created (59 differential ). In
parallel with the 2k common mode resistance, a total of
58 differential input impedance is achieved. This method
of termination is used to provide lower noise fi gure through
the use of feedback which reduces the effective noise of
the termination resistor. By adding additional resistance in
series with the termination pins, higher input impedances
can be obtained (see Table 1). The optimum impedance
for minimizing the noise fi gure of the LTC6410-6 is close
to 400. Because the amplifi er is inherently a voltage
amplifi er, the difference between the impedance at the
input and the output adds additional power gain as can
be seen in Table 1. These higher impedance levels can be
useful in interfacing with active mixers which can have
output impedance of 400 and beyond.
Input and Output Common Mode Bias
The LTC6410-6 is internally self-biased through the V
BIAS
pin (see the Block Diagram). Therefore the LTC6410-6
can be AC-coupled with no external biasing circuitry. The
output will have approximately the same common mode
voltage as the input.
In the case of a DC-coupled input connection, the input
DC common mode voltage will also set the output com-
mon mode voltage. Note that a voltage divider is formed
between the V
BIAS
buffer output and the DC input source
impedance.
The V
BIAS
pin has an internal voltage divider which will
self bias to approximately 1.4V on a 3V supply (0.47 •
V
SUPPLY
). An external capacitor of 0.1F to ground is
recommended to bypass the pin. The resistance of the pin
is 3k. See Distortion vs Common Mode graph.
For increased common mode accuracy, the +TERM and
–TERM pins can be AC-coupled to the inputs with capaci-
tors (C
EXT
). This coupling prevents the feedback from the
termination resistance from creating additional DC com-
mon mode voltage error. The G
CM
and V
OSCM
of the DC
Electrical Characteristics table refl ect the less accurate
DC-coupled scenario.
The termination inputs are part of a high speed feedback
loop. The physical length of the termination loop (R
EXT
and C
EXT
) must be minimized to maintain stability and
minimize gain peaking.
Gain
Internally, the LTC6410-6 has a voltage gain of 2.7V/V.
The default source and load resistances in most of the
data sheet are assumed to be 50 differential. Due to the
input and output resistance of the LTC6410-6 being 58
and 22 respectively, the overall voltage gain in a 50
system is 6dB (2V/V). Other source and load resistances
will produce different gains due to the resistive dividers.
Figure 1 is a system diagram for calculating gain.
Figure 1
R
IN
64106 F01
R
S
R
LOAD
LTC6410-6
R
OUT
22Ω
V
S
