Data Sheet
5V, 2A, 1.5MHz, Step-down DC-DC Converter AUR9721
Aug. 2012 Rev. 1.0 BCD Semiconductor Manufacturing Limited
9
Application Information (Continued)
5. Short Circuit Protection
When the output node is shorted to GND, as V
FB
drops under 0.4V, the chip will enter soft-start to
protect itself; when short circuit is removed, and V
FB
rises over 0.4V, AUR9721 will enter normal
operation again. If the chip reaches OCP threshold
while short circuited, it will enter soft-start cycle until
the current drops under OCP threshold.
6.
Efficiency Considerations
The efficiency of switching regulator is equal to the
output power divided by the input power times 100%.
It is usually useful to analyze the individual losses to
determine what is limiting efficiency and which
change could produce the largest improvement.
Efficiency can be expressed as:
Efficiency=100%-L1-L2-…..
Where L1, L2, etc, are the individual losses as a
percentage of input power.
Although all dissipative elements in the regulator
produce losses, two major sources usually account for
most of the power losses: V
IN
quiescent current and
I
2
R losses. The V
IN
quiescent current loss dominates
the efficiency loss at very light load currents and the
I
2
R loss dominates the efficiency loss at medium to
heavy load currents.
6.1 The V
IN
quiescent current loss comprises two
parts: the DC bias current as given in the electrical
characteristics and the internal MOSFET switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each cycle the gate is switched
from high to low, then to high again, and the packet
of charge, dQ moves from V
IN
to ground. The
resulting dQ/dt is the current out of V
IN
that is
typically larger than the internal DC bias current. In
continuous mode,
Where Q
P
and Q
N
are the gate charge of power
PMOSFET and NMOSFET switches. Both the DC
bias current and gate charge losses are proportional to
the V
IN
and this effect will be more serious at higher
input voltages.
6.2 I
2
R losses are calculated from internal switch
resistance, R
SW
and external inductor resistance R
L
.
In continuous mode, the average output current
flowing through the inductor is chopped between
power PMOSFET switch and NMOSFET switch.
Then, the series resistance looking into the SW pin is
a function of both PMOSFET R
DS(ON)P
and
NMOSFET R
DS(ON)N
resistance and the duty cycle
(D):
Therefore, to obtain the I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the
average output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for
less than 2% of total additional loss.
7. Thermal Characteristics
In most applications, the part does not dissipate much
heat due to its high efficiency. However, in some
conditions when the part is operating in high ambient
temperature with high R
DS(ON)
resistance and high
duty cycles, the heat dissipated may exceed the
maximum junction temperature. To avoid the part
from exceeding maximum junction temperature, the
user should do some thermal analysis. The maximum
power dissipation depends on the layout of PCB, the
thermal resistance of IC package, the rate of
surrounding airflow and the temperature difference
between junction and ambient.
8. PC Board Layout Considerations
When laying out the printed circuit board, the
following checklist should be used to optimize the
performance of AUR9721.
1. The power traces, including the GND trace, the SW
trace and the VIN trace should be kept direct, short and
wide.
2. Put the input capacitor as close as possible to the
VIN and GND pins.
3. The FB pin should be connected directly to the
feedback resistor divider.
4. Keep the switching node SW away from the
sensitive FB pin and the node should be kept small
area.
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1
