MAX1284BCSA+T Datasheet MAX1285BCSA+T, MAX1284BCSA+T, MAX1284BESA+T | P10-P12

MAX1284/MAX1285

400ksps/300ksps, Single-Supply, Low-Power,

Serial 12-Bit ADCs with Internal Reference

10 ______________________________________________________________________________________

Figure 5. Supply Current vs. Conversion Rate

To start a conversion, pull

low. At

CS’s

falling edge,

the T/H enters its hold mode and a conversion is initiat-

ed. Data can then be shifted out serially with the exter-

nal clock.

Using

SHDN

to Reduce Supply Current

Power consumption can be reduced significantly by

shutting down the MAX1284/MAX1285 between con-

versions. Figure 5 shows a plot of average supply cur-

rent versus conversion rate. The wake-up time (t

WAKE

)

is the time from when SHDN is deasserted to the time

when a conversion may be initiated (Figure 6). This

time depends on the time in shutdown (Figure 7)

because the external 4.7µF reference bypass capacitor

loses charge slowly during shutdown and can be as

long as 2ms.

Timing and Control

Conversion-start and data-read operations are con-

trolled by the

and SCLK digital inputs. The timing dia-

grams of Figures 8 and 9 outline serial-interface

operation.

falling edge initiates a conversion sequence: the

T/H stage holds the input voltage, the ADC begins to

convert, and DOUT changes from high impedance to

logic low. SCLK is used to drive the conversion

process, and it shifts data out as each bit of conversion

is determined.

SCLK begins shifting out the data after the rising edge

of the third SCLK pulse. DOUT transitions 20ns after

each SCLK rising edge. The third rising clock edge

produces the MSB of the conversion at DOUT, followed

by the remaining bits. Since there are twelve data bits

and three leading zeros, at least fifteen rising clock

edges are needed to shift out these bits. Extra clock

pulses occurring after the conversion result has been

clocked out, and prior to a rising edge of

, produce

trailing zeros at DOUT and have no effect on converter

operation.

Pull

high after reading the conversion’s LSB. For

maximum throughout,

can be pulled low again to

initiate the next conversion immediately after the speci-

fied minimum time (t

Output Coding and Transfer Function

The data output from the MAX1284/MAX1285 is binary,

and Figure 10 depicts the nominal transfer function.

Code transitions occur halfway between successive-

integer LSB value V

REF

= +2.5V, and 1LSB = 610µV or

2.5V/4096.

COMPLETE CONVERSION SEQUENCE

CONVERSION 0 CONVERSION 1

POWERED-UPPOWERED-UP POWERED-DOWN

WAKE

DOUT

SHDN

Figure 6. Shutdown Sequence

0.1

100

10k

0.1 101 100 1000 10,000 100,000

CONVERSION RATE (ksps)

SUPPLY CURRENT (μA)

= 3V

DOUT = FS

∞

= 10pF

MAX1284/MAX1285

400ksps/300ksps, Single-Supply, Low-Power,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 11

Applications Information

Connection to Standard Interfaces

The MAX1284/MAX1285 serial interface is fully compat-

ible with SPI/QSPI and MICROWIRE (Figure 11).

If a serial interface is available, set the CPU’s serial interface

in master mode so the CPU generates the serial clock.

Choose a clock frequency up to 6.4MHz (MAX1284) or

4.8MHz (MAX1285).

1) Use a general-purpose I/O line on the CPU to pull

low. Keep SCLK low.

2) Activate SCLK for a minimum of fifteen clock cycles.

The first two clocks produce zeros at DOUT. DOUT

output data transitions 20ns after the third SCLK rising

edge and is available in MSB-first format. Observe the

0.50

0.25

1.00

0.75

1.25

1.50

0.0001 0.010.001 0.1 1 10

TIME IN SHUTDOWN (s)

REFERENCE POWER-UP DELAY (ms)

REF

= 4.7

Figure 7. Reference Power-Up vs. Time in Shutdown

A/D STATE

DOUT

HIGH-Z

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SCLK

143 8 12 15

ACQ

HOLD/CONVERT ACQUISITION

Figure 8. Interface Timing Sequence

SCLK

DOUT

DOE

DOH

DOD

DOV

CSO

CSS

CSI

CSO

CSH

CSW

Figure 9. Detailed Serial-Interface Timing

MAX1284/MAX1285

400ksps/300ksps, Single-Supply, Low-Power,

Serial 12-Bit ADCs with Internal Reference

12 ______________________________________________________________________________________

SCLK to DOUT valid timing characteristic. Data can be

clocked into the µP on SCLK rising edge.

3) Pull

high at or after the 15th rising clock edge. If CS

remains low, trailing zeros are clocked out after the

LSB.

4) With CS = high, wait the minimum specified time, t

CS,

before initiating a new conversion by pulling CS low. If

a conversion is aborted by pulling CS high before the

conversion completes, wait for the minimum acquisition

time, t

ACQ

, before starting a new conversion.

CS must be held low until all data bits are clocked out.

Data can be output in two bytes or continuously, as

shown in Figure 8. The bytes contain the result of the

conversion padded with three leading zeros and three

trailing zeros.

SPI and MICROWIRE

When using SPI or MICROWIRE, set CPOL = 0 and

CPHA = 0. Conversion begins with a

falling edge.

DOUT goes low, indicating a conversion in progress. Two

consecutive 1-byte reads are required to get the full

twelve bits from the ADC. DOUT output data transitions

on SCLK’s rising edge and is clocked into the following

µP on the rising edge.

The first byte contains three leading zeros, and five bits of

conversion result. The second byte contains the remaining

seven bits and one trailing zero. See Figure 11 for con-

nections and Figure 12 for timing.

QSPI

Unlike SPI, which requires two 1-byte reads to acquire

the 12 bits of data from the ADC, QSPI allows the mini-

mum number of clock cycles necessary to clock in the

data. The MAX1284/MAX1285 require 15 clock cycles

from the µP to clock out the 12 bits of data. Figure 13

shows a transfer using CPOL = 0 and CPHA = 1. The

conversion result contains two zeros followed by the 12

bits of data in MSB-first formatted.

Layout, Grounding, and Bypassing

For best performance, use PC boards. Wire-wrap boards

are not recommended. Board layout should ensure that

digital and analog signal lines are separated from each

other. Do not run analog and digital (especially clock)

lines parallel to one another, or digital lines underneath

the ADC package.

11…111

11…110

11…101

00…011

00…010

00…001

00…000

012 FS

OUTPUT CODE

FS - 3/2LSBINPUT VOLTAGE (LSBs)

FS = V

REF

1LSB =

REF

4096

FULL-SCALE

TRANSITION

Figure 10. Unipolar Transfer Function, Full Scale (FS) = V

REF

Zero Scale (ZS) = GND

SCLK

DOUT

I/O

SCK

MISO

+3V TO +5V

a) SPI

SCLK

DOUT

SCK

MISO

+3V TO +5V

b) QSPI

MAX1284

MAX1285

MAX1284

MAX1285

MAX1284

MAX1285

SCLK

DOUT

I/O

c) MICROWIRE

Figure 11. Common Serial-Interface Connections to the

MAX1284/MAX1285

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

MAX1284BCSA+T

Mfr. #:

Buy MAX1284BCSA+T

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 12-Bit 400ksps 5.5V Precision ADC

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MAX1284BCSA+T

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