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74HCT7046AD/AUJ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
December 1990 19
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
VCO section
GND = 0 V; t
r
=t
f
= 6 ns; C
L
= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
OTHER+25 −40 to +85 −40 to +125
min. typ. max. typ. max. min. max.
∆f/T frequency stability
with temperature
change
0.15 %/K 4.5 V
I
=V
COIN
within
recommended
range;
R1 = 100 kΩ;
R2 = ∞;
C1 = 100 pf;
see Fig.16b
f
o
VCO centre frequency
(duty factor = 50%)
11.0 17.0 MHz 4.5 V
VCOIN
= 1/2 V
CC
;
R1 = 3 kΩ; R2 = ∞;
C1 = 40 pF;
see Fig.17
∆f
VCO
VCO frequency
linearity
0.4 % 4.5 R1 = 100 kΩ;
R2 = ∞;
C1 = 100 pF; see
Figs 18 and 19
δ
VCO
duty factor at VCO
OUT
50 % 4.5
December 1990 20
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
FIGURE REFERENCES FOR DC CHARACTERISTICS
Fig.10 Typical input resistance curve at SIG
IN
,
COMP
IN
.
Fig.11 Input resistance at SIG
IN
, COMP
IN
with
∆V
I
= 0.5 V at self-bias point.
Fig.12 Input current at SIG
IN
, COMP
IN
with
∆V
I
= 0.5 V at self-bias point.
Fig.13 Offset voltage at demodulator output as a
function of VCO
IN
and R
S
.
____ R
S
= 50 kΩ
- - - - R
S
= 300 kΩ
December 1990 21
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
AC WAVEFORMS
Fig.14 Waveforms showing input (SIG
IN
, COMP
IN
) to output (PC1
OUT
) propagation delays and the output
transition times.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
Fig.15 Waveforms showing the 3-state enable and disable times for PC2
OUT
.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

74HCT7046AD/AUJ

Mfr. #:
Buy 74HCT7046AD/AUJ
Manufacturer:
NXP Semiconductors
Description:
Phase Locked Loops - PLL Phase-locked-loop with lock detecto
Lifecycle:
New from this manufacturer.
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