11
FN9257.2
March 7, 2008
transient loading. Unfortunately, ESL is not a specified
parameter. Work with your capacitor supplier and measure
the capacitor’s impedance with frequency to select a
suitable component. In most cases, multiple electrolytic
capacitors of small case size perform better than a single
large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by Equation 15:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL8104 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient load is different for the
application of load and the removal of load. Equation 16
gives the approximate response time interval for application
and removal of a transient load:
where: I
TRAN
is the transient load current step, t
RISE
is the
response time to the application of load, and t
FALL
is the
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
output voltage setting. Be sure to check both of these
equations at the minimum and maximum output levels for
the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q
1
and the source of Q
2
.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select a bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage, a voltage rating of 1.5 times greater is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs,
solid tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surge-
current at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.
MOSFET Selection/Considerations
The ISL8104 requires at least 2 N-Channel power MOSFETs.
These should be selected based upon r
DS(ON)
, gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. At a
300kHz switching frequency, the conduction losses are the
largest component of power dissipation for both the top-side
and the bottom-side MOSFETs. These losses are distributed
between the two MOSFETs according to duty factor (see the
following equations). Only the top-side MOSFET exhibits
switching losses, since the schottky rectifier clamps the
switching node before the synchronous rectifier turns on.
Equation 17 assumes linear voltage-current transitions and
does not adequately model power loss due to the
reverse-recovery of the bottom-side MOSFETs body diode.
The gate-charge losses are dissipated by the ISL8104 and
don't heat the MOSFETs. However, large gate-charge
increases the switching interval, t
SW
which increases the
top-side MOSFET switching losses. Ensure that both
MOSFETs are within their maximum junction temperature at
high ambient temperature by calculating the temperature
rise according to package thermal-resistance specifications.
A separate heatsink may be necessary depending upon
MOSFET power, package type, ambient temperature and air
flow.
ΔV
OUT
= ΔI x ESR
ΔI =
V
IN
- V
OUT
Fs x L
--------------------------------
V
OUT
V
IN
----------------
•
(EQ. 15)
t
FALL
L
O
I
TRAN
×
V
OUT
-------------------------------
=t
RISE
L
O
I
TRAN
×
V
IN
V
OUT
–
------------------------------- -
=
(EQ. 16)
P
top-side
= I
O
2
x r
DS(ON)
x D +
1
2
Io x V
IN
x t
SW
x f
SW
P
bottom-side
= I
O
2
x r
DS(ON)
x (1 - D)
where: D is the duty cycle = V
O
/ V
IN
,
t
SW
is the switching interval, and
f
SW
is the switching frequency.
(EQ. 17)
ISL8104
