CY2509/10
Spread Aware™, Ten/Eleven Output Zero
Delay Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-07230 Rev. *G Revised November 28, 2014
Spread Aware™, Ten/Eleven Output Zero Delay Buffer
Features
■ Spread Aware™ designed to work with spread spectrum
frequency timing generator (SSFTG) reference signals
■ Well suited to both 100- and 133-MHz designs
Ten (CY2509) or eleven (CY2510) low-voltage complementary
metal oxide semiconductor (LVCMOS) / low-voltage transistor-
transistor logic (LVTTL) outputs.
■ 50 ps typical peak cycle-to-cycle jitter
■ Single output enable pin for CY2510 version, dual pins on
CY2509 devices allow shutting down a portion of the outputs
■ 3.3 V power supply
■ On-chip 25 : damping resistors
■ Available in 24-pin thin shrunk small outline package (TSSOP)
package
■ Improved tracking skew, but narrower frequency support limit
when compared to W132-09B/10B
Key Specifications
Operating voltage: .............................................3.3 V ± 10%
Operating range: ..........................40 MHz < f
OUT
< 140 MHz
Cycle-to-cycle jitter: ..................................................<100 ps
Output to output skew: ..............................................<100 ps
Phase error jitter: .......................................................<100 ps
For a complete list of related documentation, click here.
Q0
PLL
Q1
Q2
Q3
Q5
Q6
OE0:4
Q7
Q8
FBOUT
Q4
Q9
OE
OE5:8
Configuration of these blocks dependent upon specific option being used
FBIN
CLK
24
23
22
21
20
19
18
17
16
15
14
13
AGND
VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
CY2510
24
23
22
21
20
19
18
AGND
VDD
Q0
Q1
Q2
GND
GND
1
2
3
4
5
6
7
CY2509
Logic Block Diagram
