CY2509ZXC-1T Datasheet CY2510ZXC-1, CY2509ZXC-1, CY2510ZXC-1T | P4-P6

CY2509/10

Document Number: 38-07230 Rev. *G Page 4 of 12

Functional Overview

The CY2509/10 is a PLL-based clock driver designed for use in

dual inline memory modules. The clock driver has output

frequencies of up to 133 MHz and output to output skews of less

than 250 ps. The CY2509/10 provides minimum cycle-to-cycle

and long-term jitter, which is of significant importance to meet the

tight input-to-input skew budget in DIMM applications.

The current generation of 256- and 512-megabyte memory

modules needs to support 100-MHz clocking speeds. Especially

for cards configured in 16x4 or 8x8 format, the clock signal

provided from the motherboard is generally not strong enough to

meet all the requirements of the memory and logic on the DIMM.

The CY2509/10 takes in the signal from the motherboard and

buffers out clock signals with enough drive to support all the

DIMM board clocking needs. The CY2509/10 is also designed to

meet the needs of new PC133 SDRAM designs, operating to

133 MHz.

The CY2509/10 was specifically designed to accept SSFTG

signals currently being used in motherboard designs to reduce

EMI. Zero delay buffers which are not designed to pass this

feature through may cause skewing failures.

Output enable pins allow for shutdown of output when they are

not being used. This reduces EMI and power consumption.

Pin Definitions

Pin Name

Pin No.

(2509)

Pin No.

(2510)

Pin Type Pin Description

CLK 24 24 I Reference input: Output signals Q0:9 will be synchronized to this signal.

FBIN 13 13 I Feedback input: This input must be fed by one of the outputs (typically FBOUT)

to ensure proper functionality. If the trace between FBIN and FBOUT is equal in

length to the traces between the outputs and the signal destinations, then the

signals received at the destinations will be synchronized to the CLK signal input.

Q0:8 3, 4, 5, 8, 9,

16, 17, 20,

3, 4, 5, 8, 9,

15, 16, 17,

O Integrated series resistor outputs: The frequency and phase of the signals

provided by these pins will be equal to the reference signal if properly laid out.

Each output has a 25 : series damping resistor integrated.

Q9 n/a 21 O Integrated series resistor output: The frequency and phase of the signal

provided by this pin will be equal to the reference signal if properly laid out. This

output has a 25: series damping resistor integrated.

FBOUT 12 12 O Feedback output: This output has a 25 : series resistor integrated on chip.

Typically it is connected directly to the FBIN input with a trace equal in length to

the traces between outputs Q0:9 and the destination points of these output

signals.

AVDD 23 23 P Analog power connection: Connect to 3.3 V. Use ferrite beads to help reduce

noise for optimal jitter performance.

AGND 1 1 G Analog ground connection: Connect to common system ground plane.

VDD 2, 10, 15,

2, 10, 14,

P Power connections: Connect to 3.3 V. Use ferrite beads to help reduce noise

for optimal jitter performance.

GND 6, 7, 18, 19 6, 7, 18, 19 G Ground connections: Connect to common system ground plane.

OE n/a 11 I Output enable input: Tie to V

(HIGH, 1) for normal operation. When brought

to GND (LOW, 0) all outputs are disabled to a LOW state.

OE0:4 11 n/a I Output enable input: Tie to V

(HIGH, 1) for normal operation. When brought

to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state.

OE5:8 14 n/a I Output enable input: Tie to V

(HIGH, 1) for normal operation. When brought

to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state.

CY2509/10

Document Number: 38-07230 Rev. *G Page 5 of 12

Spread Aware™

Many systems being designed now utilize a technology called

Spread Spectrum Frequency Timing Generation. Cypress has

been one of the pioneers of SSFTG development, and we

designed this product so as not to filter off the Spread Spectrum

feature of the Reference input, assuming it exists. When a zero

delay buffer is not designed to pass the SS feature through, the

result is a significant amount of tracking skew which may cause

problems in systems requiring synchronization.

For more details on Spread Spectrum timing technology, please

see the Cypress application note titled, “EMI Suppression

Techniques with SSFTG ICs.”

How to Implement Zero Delay

Typically, Zero Delay Buffers (ZDBs) are used because a

designer wants to provide multiple copies of a clock signal in

phase with each other. The whole concept behind ZDBs is that

the signals at the destination chips are all going HIGH at the

same time as the input to the ZDB. In order to achieve this, layout

must compensate for trace length between the ZDB and the

target devices. The method of compensation is described below.

External feedback is the trait that allows for this compensation.

Since the PLL on the ZDB will cause the feedback signal to be

in phase with the reference signal. When laying out the board,

match the trace lengths between the output being used for feed

back and the FBIN input to the PLL.

If it is desirable to either add a little delay, or slightly precede the

input signal, this may also be affected by either making the trace

to the FBIN pin a little shorter or a little longer than the traces to

the devices being clocked.

Inserting Other Devices in Feedback Path

Another nice feature available due to the external feedback is the

ability to synchronize signals up to the signal coming from some

other device. This implementation can be applied to any device

(ASIC, multiple output clock buffer/driver, etc.) which is put into

the feedback path.

Referring to Figure 2, if the traces between the ASIC/buffer and

the destination of the clock signal(s) (A) are equal in length to the

trace between the buffer and the FBIN pin, the signals at the

destination(s) device will be driven HIGH at the same time the

Reference clock provided to the ZDB goes HIGH. Synchronizing

the other outputs of the ZDB to the outputs form the ASIC/Buffer

is more complex however, as any propagation delay in the

ASIC/Buffer must be accounted for.

Figure 1. CY2510 Example Schematic

GND

AGND

FBIN

VDD

AVDD

CLK

FBOUT

VDD

0.1

3.3V

CY2510

0.1

Figure 2. Additional Buffering Feedback Path Example

Schematic

Reference

Signal

Feedback

Input

ASIC/

Buffer

Zero

Delay

Buffer

CY2509/10

Document Number: 38-07230 Rev. *G Page 6 of 12

Absolute Maximum Ratings

Stresses greater than those listed in Absolute Maximum Ratings

[1]

table may cause permanent damage to the device. These

represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections

of this specification is not implied. Maximum conditions for extended periods may affect reliability.

Parameter Description Min Max Unit

, V

Voltage on any pin with respect to GND –0.5 +7.0 V

STG

Storage temperature –65 +150 °C

Operating temperature 0 +70 °C

Ambient temperature under bias –55 +125 °C

Power dissipation 0.5 – W

DC Electrical Characteristics

= 0 °C to 70 °C, V

= 3.3 V ±10%

Parameter Description Test Condition Min Typ Max Unit

Supply current Unloaded, 100 MHz – – 200 mA

Input low voltage – – 0.8 V

Input high voltage 2.0 – V

+ 0.3 V

Output low voltage I

= 12 mA – – 0.8 V

Output high voltage I

= –12 mA 2.1 – – V

Input low current V

= 0 V – – 50 PA

Input high current V

= V

––50PA

Note

1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

P1-P3 P4-P6 P7-P9 P10-P12

CY2509ZXC-1T

Mfr. #:

Buy CY2509ZXC-1T

Manufacturer:

Cypress Semiconductor

Description:

IC CLK ZDB 10OUT 140MHZ 24TSSOP

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CY2509ZXC-1T

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