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NL17SZ00P5T5G

P1-P3P4-P6P7-P9
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 13
1 Publication Order Number:
NL17SZ00/D
NL17SZ00
Single 2-Input NAND Gate
The NL17SZ00 is a single 2−input NAND Gate in three tiny
footprint packages. The device performs much as LCX multi−gate
products in speed and drive.
Features
• Tiny SOT−353, SOT−553 and SOT−953 Packages
• 2.7 ns T
PD
at 5 V (typ)
• Source/Sink 24 mA at 3.0 V
• Over−Voltage Tolerant Inputs
• Pin For Pin with NC7SZ00P5X, TC7SZ00FU and TC7SZ00AFE
• Chip Complexity: FETs = 20
• Designed for 1.65 V to 5.5 V V
CC
Operation
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Figure 1. Pinouts (Top View)
Figure 2. Logic Symbol
&
OUT Y
IN A
IN B
V
CC
IN A
IN B
1
2
3
5
4
GND
OUT Y
V
CC
IN B
IN A
OUT Y
GND
1
2
3
5
4
6
NC
SOT−353/SC70−5/
SC−88A/SOT−553
UDFN
V
CC
IN B
IN A
OUT Y
GND
1
2
3
4
5
SOT−953
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
MARKING
DIAGRAMS
L1 MG
G
SOT−553
XV5 SUFFIX
CASE 463B
L1 = Specific Device Marking
M = Date Code
L1 M
SOT−353/SC70−5/SC−88A
DF SUFFIX
CASE 419A
1
5
ORDERING INFORMATION
1
5
1
5
1
5
www.onsemi.com
L1 = Specific Device Marking
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
1
M
UDFN6
1.45 x 1.0
CASE 517AQ
X M
1
UDFN6
1.0 x 1.0
CASE 517BX
X = Specific Device Marking
M = Date Code
SOT−953
CASE 527AE
T = Specific Device Code
M = Month Code
T M
1
F
NL17SZ00
www.onsemi.com
2
PIN ASSIGNMENT (SOT−353/
SC70−5/SC−88A/SOT−553/ UDFN)
Pin
1
2
3
4
5
Function
IN A
IN B
GND
OUT Y
V
CC
Input
FUNCTION TABLE
B
L
H
L
H
Output
Y = AB
Y
H
H
H
L
A
L
L
H
H
PIN ASSIGNMENT (SOT−953)
Pin
1
2
3
4
5
Function
IN A
GND
IN B
OUT Y
V
CC
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage −0.5 to + 7.0 V
V
IN
DC Input Voltage −0.5 to + 7.0 V
V
OUT
DC Output Voltage
(SOT−353/SC70−5/SC−88A/SOT−553/UDFN Packages) Power−Down Mode
−0.5 to + 7.0 V
V
OUT
DC Output Voltage
(SOT−953 Package)
−0.5 to V
CC
+ 0.5 V
I
IK
DC Input Diode Current −50 mA
I
OK
DC Output Diode Current V
OUT
< GND, V
OUT
> V
CC
(SOT−953 Package)
±50 mA
I
OK
DC Output Diode Current V
OUT
< GND
(SOT−353/SC70−5/SC−88A/SOT−553 Packages)
−50 mA
I
OUT
DC Output Current ±50 mA
I
CC
DC Supply Current per Supply Pin ±100 mA
T
STG
Storage Temperature Range −65 to + 150 °C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260 °C
T
J
Junction Temperature Under Bias +150 °C
q
JA
Thermal Resistance SOT−353 (Note 1)
SOT−553
350
496
°C/W
P
D
Power Dissipation in Still Air at 85°C SOT−353
SOT−553
186
135
mW
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
ESD ESD Classification Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
2000
200
N/A
I
LATCHUP
Latchup Performance Above V
CC
and Below GND at 125°C (Note 5) ±100 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A, rated to EIA/JESD22−A114−B.
3. Tested to EIA/JESD22−A115−A, rated to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
NL17SZ00
www.onsemi.com
3
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 1.65 5.5 V
V
IN
DC Input Voltage 0 5.5 V
V
OUT
DC Output Voltage
(SOT−353/SC70−5/SC−88A/SOT−553/UDFN Packages)
0 5.5 V
V
OUT
DC Output Voltage (SOT−953 Package) 0 V
CC
V
T
A
Operating Temperature Range −55 +125 °C
t
r
, t
f
Input Rise and Fall Time V
CC
= 3.0 V ± 0.3 V
V
CC
= 5.0 V ± 0.5 V
0
0
100
20
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbo
l
Parameter Condition
V
CC
(V)
T
A
= 255C −555C v T
A
v 1255C
Uni
t
Min Typ Max Min Max
V
IH
High−Level Input Voltage 1.65 to 1.95
2.3 to 5.5
0.75 V
CC
0.7 V
CC
0.75 V
CC
0.7 V
CC
V
V
IL
Low−Level Input Voltage 1.65 to 1.95
2.3 to 5.5
0.25 V
CC
0.3 V
CC
0.25 V
CC
0.3 V
CC
V
V
OH
High−Level Output Voltage
V
IN
= V
IL
or V
IH
I
OH
= −100 mA
I
OH
= −3 mA
I
OH
= −8 mA
I
OH
= −12 mA
I
OH
= −16 mA
I
OH
= −24 mA
I
OH
= −32 mA
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
V
CC
− 0.1
1.29
1.9
2.2
2.4
2.3
3.8
V
CC
1.4
2.1
2.4
2.7
2.5
4.0
V
CC
− 0.1
1.29
1.9
2.2
2.4
2.3
3.8
V
V
OL
Low−Level Output Voltage
V
IN
= V
IH
or V
OH
I
OL
= 100 mA
I
OL
= 3 mA
I
OL
= 8 mA
I
OL
= 12 mA
I
OL
= 16 mA
I
OL
= 24 mA
I
OL
= 32 mA
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
0.08
0.20
0.22
0.28
0.38
0.42
0.1
0.24
0.3
0.4
0.4
0.55
0.55
0.1
0.24
0.3
0.4
0.4
0.55
0.55
V
I
IN
Input Leakage Current V
IN
= 5.5 V or GND 0 to 5.5 ±0.1 ±1.0
mA
I
OFF
Power Off Leakage
Current
V
IN
= 5.5 V or
V
OUT
= 5.5 V
0 1 10
mA
I
CC
Quiescent Supply Current V
IN
= 5.5 V or GND 5.5 1 10
mA
AC ELECTRICAL CHARACTERISTICS t
R
= t
F
= 3.0 ns
Symbo
l
Parameter Condition
V
CC
(V)
T
A
= 255C −555C v T
A
v 1255C
Uni
t
Min Typ Max Min Max
t
PLH
t
PHL
Propagation Delay
(Figure 3 and 4)
R
L
= 1 MW, C
L
= 15 pF
1.65 2.0 5.4 11.4 2.0 12
ns
R
L
= 1 MW, C
L
= 15 pF
1.8 2.0 4.5 9.5 2.0 10.0
R
L
= 1 MW, C
L
= 15 pF
2.5 to 0.2 0.8 3.0 6.5 0.8 7.0
R
L
= 1 MW, C
L
= 15 pF
3.3 ± 0.3
0.5 2.4 4.5 0.5 4.7
R
L
= 500 W, C
L
= 50 pF
1.5 2.4 5.0 1.5 5.2
R
L
= 1 MW, C
L
= 15 pF
5.0 ± 0.5
0.5 2.0 3.9 0.5 4.1
R
L
= 500 W, C
L
= 50 pF
0.8 2.4 4.3 0.8 4.5
P1-P3P4-P6P7-P9

NL17SZ00P5T5G

Mfr. #:
Buy NL17SZ00P5T5G
Manufacturer:
ON Semiconductor
Description:
Logic Gates SINGLE 2-INPUT NAND GATE
Lifecycle:
New from this manufacturer.
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