ICS3771G-18LF

DATASHEET
DTV, STB CLOCK SOURCE ICS3771-18
IDT™ / ICS™
DTV, STB CLOCK SOURCE 1
ICS3771-18 REV B 111307
Description
The ICS3771-18 provides clock generation and
conversion for clock rates commonly needed in HDTV
digital video equipment. The ICS3771-18 uses the
latest PLL technology to provide excellent phase noise
and long term jitter performance for superior
synchronization and S/N ratio.
For audio sampling clocks generated from 27 MHz, use
the ICS661.
Please contact IDT if you have a requirement for an
input and output frequency not included in this
document. IDT can rapidly modify this product to meet
special requirements.
Features
Integrated Phase-Lock Loop
Low jitter, high accuracy outputs
3.3 V operation
Packaged in 16-pin TSSOP
RoHS 6 (green and lead free) compliant packaging
Exact (0 ppm) multiplication ratios
Pin compatible to CY24204-3
Block Diagram
PLL Clock
Synthesis
CLKIN
VDD
CLK1
GND
OE
FS1:0
2
VDDL AVDD
27 MHz
2
CLK2
REFOUT1
REFOUT2
GNDA
Output
Multiplexer
and Dividers
ICS3771-18
DTV, STB CLOCK SOURCE SYNTHESIZERS
IDT™ / ICS™
DTV, STB CLOCK SOURCE 2
ICS3771-18 REV B 111307
Pin Assignment
16-pin TSSOP
Output Clock Selection Table (MHz)
*OFF = output is driven HIGH.
Pin Descriptions
12
1
11
2
10
CLKIN
NC
3
9
VDD
4
AVDD
OE
5
NC
6
FS1
7
GNDA
8
GND
GND
CLK1
VDDL
REFOUT2
FS0
REFOUT1
CLK2
16
15
14
13
OE FS1 FS0 CLK1/CLK2 REFOUT1/REFOUT2
000 OFF* 27
001 OFF* 27
010 OFF* 27
011 OFF* 27
1 0 0 27 27
1 0 1 27.027 27
1 1 0 74.250 27
1 1 1 74.17582418 27
Pin
Numbe
r
Pin
Name
Pin
Type
Pin Description
1 CLKIN Input Reference clock input. Connect to a 27 MHz external clock.
2 VDD Power Power supply.
3 AVDD Power Power supply. Connect to 3.3 V.
4 NC No connect. Leave floating.
5 GNDA Power Analog ground.
6 GND Power Connect to ground.
7 REFOUT Output Reference Clock output 2. See table above.
8 REFOUT Output Reference Clock output 1. See table above.
9 CLK2 Output Selectable Clock output 2. See table above.
10 FS0 Input Frequency select pin 0. Weak internal pull-up. See table above.
11 VDDL Power Power supply. Connect to 3.3 V.
12 CLK1 Output Selectable Clock output 1. See table above
13 GND Power Connect to ground.
14 FS1 Input Frequency select pin 1. Weak internal pull-up. See table above.
15 OE Output Output Enable pin. Weak internal pull-up. See table above.
16 NC No connect. Leave floating.
ICS3771-18
DTV, STB CLOCK SOURCE SYNTHESIZERS
IDT™ / ICS™
DTV, STB CLOCK SOURCE 3
ICS3771-18 REV B 111307
Application Information
Series Termination Resistor
Clock output traces should use series termination. To
series terminate a 50 trace (a commonly used trace
impedance), place a 33 resistor in series with the
clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS3771-18 must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the ICS3771-18 should use one common connection to
the PCB power plane as shown in the diagram on the
next page. The ferrite bead and bulk capacitor help
reduce lower frequency noise in the supply that can
lead to output clock phase modulation.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via. Distance of the
ferrite bead and bulk decoupling from the device is less
critical.
2) The external crystal should be mounted next to the
device with short traces. The X1 and X2 traces should
not be routed next to each other with minimum spaces,
instead they should be separated and away from other
traces.
3) To minimize EMI and obtain the best signal integrity,
the 33 series termination resistor should be placed
close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS3771-18.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.

ICS3771G-18LF

Mfr. #:
Manufacturer:
Description:
IC CLK SOURCE DTV/STB 16-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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