ADA4411-3
Rev. 0 | Page 11 of 16
APPLICATIONS
OVERVIEW CUTOFF FREQUENCY SELECTION
With its high impedance multiplexed inputs and high output
drive, the ADA4411-3 is ideally suited to video reconstruction
and antialias filtering applications. The high impedance inputs
give designers flexibility with regard to how the input signals
are terminated. Devices with DAC current source outputs that
feed the ADA4411-3 can be loaded in whatever resistance
provides the best performance, and devices with voltage outputs
can be optimally terminated as well. The ADA4411-3 outputs
can each drive up to two source-terminated 75 Ω loads and can
therefore directly drive the outputs from set-top boxes, DVD
players, and the like without the need for a separate output
buffer.
Four combinations of cutoff frequencies are provided for the
video signals. The cutoff frequencies have been selected to
correspond with the most commonly deployed component
video scanning systems. Selection between the cutoff frequency
combinations is controlled by the logic signals applied to the
F_SEL_A and F_SEL_B inputs.
Table 7 summarizes cutoff
frequency selection.
Table 7. Filter Cutoff Frequency Selection
F_SEL_A F_SEL_B Y/G Cutoff Pb/B Cutoff Pr/R Cutoff
0 0 36 MHz 36 MHz 36 MHz
Binary control inputs are provided to select cutoff frequency,
throughput gain, and input signal. These inputs are compatible
with 3 V and 5 V TTL and CMOS logic levels referenced to
GND. The disable feature is asserted by pulling the DISABLE
pin to the positive supply.
The LEVEL1 and LEVEL2 inputs comprise a differential input
that controls the dc level at the output pins.
MULTIPLEXER SELECT INPUTS
Selection between the two multiplexer inputs is controlled by
the logic signals applied to the MUX inputs.
Table 6
summarizes the multiplexer operation.
THROUGHPUT GAIN
The throughput gain of the ADA4411-3 signal paths can
be either × 2 or × 4. Gain selection is controlled by the logic
signal applied to the G_SEL pin.
Table 6 summarizes how the
gain is selected.
DISABLE
The ADA4411-3 includes a disable feature that can be used
to save power when a particular device is not in use. As
indicated in the
Overview section, the disable feature is
asserted by pulling the DISABLE pin to the positive supply.
Table 6 summarizes the disable feature operation. The
DISABLE pin also functions as a reference level for the logic
inputs and therefore must be connected to ground when the
device is not disabled.
Table 6. Logic Pin Function Description
DISABLE MUX G_SEL
V
S+
= Disabled 1 = Channel 1 Selected 1 = ×2 Gain
GND = Enabled 0 = Channel 2 Selected 0 = ×4 Gain
0 1 36 MHz 18 MHz 18 MHz
1 0 18 MHz 18 MHz 18 MHz
1 1 9 MHz 9 MHz 9 MHz
OUTPUT DC OFFSET CONTROL
The LEVEL1 and LEVEL2 inputs work as a differential, input-
referred output offset control. In other words, the output offset
voltage of a given channel is equal to the difference in voltage
between the LEVEL1 and LEVEL2 inputs, multiplied by the
overall filter gain. This relationship is expressed in Equation 1.
(1) ))(()( GLEVELLEVELOUTV
OS
21−=
LEVEL1 and LEVEL2 are the voltages applied to the respective
inputs, and G is the throughput gain.
For example, with the G_SEL input set for ×2 gain, setting
LEVEL1 to 300 mV and LEVEL2 to 0 V shifts the offset voltages
at the ADA4411-3 outputs to 600 mV. This particular setting
can be used in most single-supply applications to keep the
output swings safely above the negative supply rail.
The maximum differential voltage that can be applied across the
LEVEL1 and LEVEL2 inputs is ±500 mV. From a single-ended
standpoint, the LEVEL1 and LEVEL2 inputs have the same
range as the filter inputs. See the
Specifications tables for the
limits. The LEVEL1 and LEVEL2 inputs must each be bypassed
to GND with a 0.1 µF ceramic capacitor.
In single-supply applications, a positive output offset must be
applied to keep the negative-most excursions of the output
signals above the specified minimum output swing limit.
