16
FN6288.5
October 7, 2008
components that connect to sensitive nodes or supply critical
bypassing current and signal coupling.
Equally important are the connections of the internal gate
drives (UGATE, LGATE, PHASE, PGND, BOOT): since they
drive the power train MOSFETs using short, high current
pulses, it is important to size them accordingly and reduce
their overall impedance. While not always esthetically
pleasing, straightest connections encircling the least area
result in the lowest parasitic inductance build-up, and,
consequentially, are the better choice.
The power train components should be placed first. Locate
the input capacitors close to the power switches. Minimize
the length of the connections between the input capacitors,
C
IN
, especially the high frequency decoupling, and the
power switches. Locate the output inductor and output
capacitors between the MOSFETs and the load. Locate all
the high-frequency decoupling capacitors (ceramics) as
close as practicable to their decoupling target, making use of
the shortest connection paths to any internal planes, such as
vias to GND immediately next, or even onto the capacitor’s
grounded solder pad.
The critical small signal components include the bypass
capacitors for VIN, VCC and PVCC. Locate the bypass
capacitors, C
BP
, close to the device. It is especially
important to locate the components associated with the
feedback circuit close to their respective controller pins,
since they belong to a high-impedance circuit loop, sensitive
to EMI pick-up. Place all the other highlighted components
close to the respective pins of the ISL6540A.
A multi-layer printed circuit board is recommended. Figure 8
shows the connections of the critical components of the
converter. Note that capacitors C
xxIN
and C
xxOUT
could each
represent numerous physical capacitors. Dedicate one solid
layer, usually the one underneath the component side of the
board, to a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into smaller
islands of common voltage levels. Keep the PHASE island as
small as practicable, while still allowing for proper heat-sinking
of the lower MOSFET. The power plane should support the
input power and output power nodes. Use copper-filled
polygons on the top and bottom circuit layers for large
current-carrying circuit nodes. Use the remaining printed
circuit layers for small signal wiring.
Size the trace interconnects commensurate with the signals
they are carrying. Use narrow (0.004” to 0.008”) and short
traces for the high-impedance, small-signal connections, such
as the feedback, compensation, soft-start, frequency set,
reference input, offset, etc. The wiring traces from the IC to
the MOSFETs’ gates and sources should be wide (0.02” to
0.05”) and short, encircling the smallest area possible.
The metal pad of the ISL6540A’s package should be
connected to the ground plane via 6 to 9 small vias evenly
placed in the bottom pad’s footprint. The GND and PGND
pins should be connected to this bottom pad to find a
convenient, low inductance path to the rest of the circuitry.
This recommended connection provides not only an
electrically low impedance path, but a low thermal path as
well, helping with the heat dissipation taking place in the
part.
Compensating the Converter
The ISL6540A single-phase converter is a voltage-mode
controller. This section highlights the design considerations for
a voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended (see Figure 7).
FIGURE 7. COMPENSATION CONFIGURATION FOR
ISL6540A WHEN USING DIFFERENTIAL REMOT
E
SENSE
ISL6540A
COMP
C
1
R
2
R
1
FB
VMON
C
2
R
3
C
3
ISL6540A
17
FN6288.5
October 7, 2008
VIA CONNECTION TO GROUND PLANE
ISLAND ON/POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
KEY
LOCATE CLOSE TO IC
FIGURE 8. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
LOCATE NEAR LOAD
(MINIMIZE CONNECTION PATH)
(C
HFIN
)
C
BIN
(C
HFOUT
)
C
BOUT
R
1
C
1
HEAVY TRACE ON CIRCUIT PLANE LAYER
LOCATE NEAR SWITCHING TRANSISTORS
(MINIMIZE CONNECTION PATH)
(MINIMIZE CONNECTION PATH)
R
FB
R
OS
ISL6540A
Q1
Q2
COMP
FB
GND
VCC
BOOT
UGATE
LSOC
LGATE
L
IN
L
OUT
C
BOOT
R
LSOC
R
2
C
2
(C
F1
)
D
BOOT
PHASE
V
OUT
PVCC
(C
F2
)
REFIN
EN
OFS+
MARCTRL
OFS-
SS
REFOUT
R
OFS+
R
OFS-
C
SS
R
FS
FS
VIN
R
CC
R
HSOC
C
HSOC
HSOC
VSEN-
C
PG_DLY
C
3
R
3
PG
PG_DLY
+3.3V TO +20V
INTERNAL BIAS
LINEAR REGULATOR
VMON
VSEN+
C
SEN
LINDRV
R
MARG
VFF
VCC
V
SENSE-
V
SENSE+
(C
F3
)
C
LSOC
PGND
R
VIN
C
VFF
R
VFF
R
LS-
R
LS+
ISL6540A
18
FN6288.5
October 7, 2008
Figure 9 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, when using an internal
differential remote sense amplifier. The output voltage
(V
OUT
) is regulated to the reference voltage, VREF, level.
The error amplifier output (COMP pin voltage) is compared
with the oscillator (OSC) triangle wave to provide a
pulse-width modulated wave with an amplitude of V
IN
at the
PHASE node. The PWM wave is smoothed by the output
filter (L and C). The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
COMP
. This function is dominated by a
DC gain, given by D
MAX
V
IN
/V
OSC
, and shaped by the
output filter, with a double pole break frequency at F
LC
and a
zero at F
CE
. For the purpose of this analysis C and ESR
represent the total output capacitance and its equivalent
series resistance.
The compensation network consists of the error amplifier
(internal to the ISL6540A) and the external R
1
thru R
3
, C
1
thru
C
3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
0
; typically 0.1 to 0.3 of F
SW
) and adequate
phase margin (better than 45°). Phase margin is the
difference between the closed loop phase at F
0dB
and 180°.
The equations that follow relate the compensation network’s
poles, zeros and gain to the components (R
1
, R
2
, R
3
, C
1
, C
2
,
and C
3
) in Figures 7 and 9. Use the following guidelines for
locating the poles and zeros of the compensation network:
1. Select a value for R
1
(1kΩ to 10kΩ, typically). Calculate
value for R
2
for desired converter bandwidth (F
0
). If
setting the output voltage to be equal to the reference set
voltage as shown in Figure 7, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 9), in order
to compensate for the attenuation introduced by the
resistor divider, the below obtained R
2
value needs be
multiplied by a factor of (R
OS
+R
FB
)/R
OS
. The remainder
of the calculations remain unchanged, as long as the
compensated R
2
value is used.
A small capacitor,
C
SEN
in Figure 9, can be added to filter
out noise, typically
C
SEN
is chosen so the corresponding
time constant does not reduce the overall phase margin
of the design, typically this is 2x to 10x switching
frequency of the regulator. As the ISL6540A supports
100% duty cycle, d
MAX
equals 1. The ISL6540A also
uses feedforward compensation, as such V
OSC
is equal
to 0.16 multiplied by the voltage at the VFF pin. When
tieing VFF to V
IN
, the Equation 12 simplifies to:
2. Calculate C
1
such that F
Z1
is placed at a fraction of the F
LC
,
at 0.1 to 0.75 of F
LC
(to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
CE
/F
LC
, the lower the F
Z1
frequency (to maximize phase boost at F
LC
).
3. Calculate C
2
such that F
P1
is placed at F
CE
.
4. Calculate R
3
such that F
Z2
is placed at F
LC
. Calculate C
3
such that F
P2
is placed below F
SW
(typically, 0.5 to 1.0
times F
SW
). F
SW
represents the regulator’s switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
P2
lower in frequency
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
FIGURE 9. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
-
+
E/A
VREF
COMP
C
1
R
2
R
1
FB
C
2
R
3
C
3
L
C
V
IN
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
OSCILLATOR
ESR
EXTERNAL CIRCUITISL6540A
V
OUT
V
OSC
DCR
UGATE
PHASE
LGATE
-
+
VMON
VSEN+
VSEN-
C
SEN
R
OS
R
FB
F
LC
1
2π LC
---------------------------
=
F
CE
1
2π C ESR⋅⋅
---------------------------------
=
(EQ. 10)
R
2
V
OSC
R
1
F
0
⋅⋅
d
MAX
V
IN
F
LC
⋅⋅
---------------------------------------------
=
(EQ. 11)
R
2
0.16 R
1
F
0
⋅⋅
F
LC
----------------------------------
=
(EQ. 12)
C
1
1
2π R
2
0.5 F
LC
⋅⋅
-----------------------------------------------
=
(EQ. 13)
C
2
C
1
2π R
2
C
1
F
CE
1⋅⋅⋅
--------------------------------------------------------
=
(EQ. 14)
ISL6540A

ISL6540ACRZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers PB FREE 3 3V-20V INPUT SYNC PWM CONT
Lifecycle:
New from this manufacturer.
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