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74LV595N,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
74LV595_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 21 April 2009 4 of 20
NXP Semiconductors
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 6. Pin configuration DIP16, SO16 Fig 7. Pin configuration SSOP16, TSSOP16
74LV595
Q1 V
CC
Q2 Q0
Q3 DS
Q4 OE
Q5 STCP
Q6 SHCP
Q7 MR
GND Q7S
001aaj970
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74LV595
Q1 V
CC
Q2 Q0
Q3 DS
Q4 OE
Q5 STCP
Q6 SHCP
Q7 MR
GND Q7S
mla001
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
Q0 to Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output
GND 8 ground (0 V)
Q7S 9 serial data output
MR 10 master reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input
OE 13 output enable input (active LOW)
DS 14 serial data input
V
CC
16 supply voltage
74LV595_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 21 April 2009 5 of 20
NXP Semiconductors
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
7. Functional description
[1] H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition; X = don’t care; NC = no change;
Z = high-impedance OFF-state.
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP16 packages: above 70 °C the value of P
tot
derates linearly with 12 mW/K.
For SO16 packages: above 70 °C the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60 °C the value of P
tot
derates linearly with 5.5 mW/K.
Table 3. Function table
[1]
Input Output Function
SHCP STCP OE MR DS Q7S Qn
X X L L X L NC a LOW-state on
MR only affects the shift register
X ↑ L L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state
↑ X L H H Q6S NC logic HIGH-state shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
X ↑ L H X NC QnS contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
↑↑L H X Q6S QnS contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage −0.5 +4.6 V
I
IK
input clamping current V
I
< −0.5 V or V
I
> +0.5 V - ±20 mA
I
OK
output clamping current V
I
< −0.5 V or V
I
> +0.5 V - ±50 mA
I
O
output current −0.5 V < V
O
<V
CC
+ 0.5 V -
standard driver outputs 25 mA
bus driver outputs 35 mA
I
CC
supply current standard driver outputs 50 mA
bus driver outputs 70 mA
I
GND
ground current standard driver outputs −50 mA
bus driver outputs −70 mA
T
stg
storage temperature −65 +150 °C
P
tot
total power dissipation T
amb
= −40 °C to +125 °C
[2]
DIP16 - 750 mW
SO16, SSOP16, TSSOP16 - 500 mW
74LV595_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 21 April 2009 6 of 20
NXP Semiconductors
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
9. Recommended operating conditions
10. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
V
CC
supply voltage 1.0 3.3 3.6 V
V
I
input voltage 0 - V
CC
V
V
O
output voltage 0 - V
CC
V
T
amb
ambient temperature −40 - +125 °C
∆t/∆V input transition rise and fall rate V
CC
= 1.0 V to 2.0 V - - 500 ns/V
V
CC
= 2.0 V to 2.7 V - - 200 ns/V
V
CC
= 2.7 V to 3.6 V - - 100 ns/V
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ
[1]
Max Min Max
V
IH
HIGH-level
input voltage
V
CC
= 1.2 V 0.9 - - 0.9 - V
V
CC
= 2.0 V 1.4 - - 1.4 - V
V
CC
= 2.7 V to 3.6 V 2.0 - - 2.0 - V
V
IL
LOW-level
input voltage
V
CC
= 1.2 V - - 0.3 - 0.3 V
V
CC
= 2.0 V - - 0.6 - 0.6 V
V
CC
= 2.7 V to 3.6 V - - 0.8 - 0.8 V
V
OH
HIGH-level
output voltage
all outputs; V
I
=V
IH
or V
IL
;
I
O
= −100 µA;
V
CC
= 1.2 V - 1.2 - - - V
V
CC
= 2.0 V 1.8 2.0 - 1.8 - V
V
CC
= 2.7 V 2.5 2.7 - 2.5 - V
V
CC
= 3.0 V 2.8 3.0 - 2.8 - V
standard outputs;
V
I
=V
IH
or V
IL
; I
O
= −6 mA;
V
CC
= 3.0 V
2.4 2.82 - 2.2 - V
bus outputs; V
I
=V
IH
or V
IL
;
I
O
= −8 mA;
V
CC
= 3.0 V
2.4 2.82 - 2.2 - V
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74LV595N,112

Mfr. #:
Buy 74LV595N,112
Manufacturer:
NXP Semiconductors
Description:
IC 8BIT SHIFT REGISTER 16-DIP
Lifecycle:
New from this manufacturer.
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