ISL84515IHZ-T

10
FN6025.5
June 9, 2014
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Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ISL84514: 40
ISL84515: 40
PROCESS:
Si Gate CMOS
FIGURE 13. FREQUENCY RESPONSE
FIGURE 14. OFF-ISOLATION
Typical Performance Curves T
A
= +25°C, Unless Otherwise Specified (Continued)
FREQUENCY (MHz)
0
-3
-6
NORMALIZED GAIN (dB)
GAIN
PHASE
0
20
40
60
80
100
PHASE (°)
1 10 100 600
V
IN
= 0.2V
P-P
to 2.5V
P-P
(V+ = 3.3V)
V
IN
= 0.2V
P-P
to 5V
P-P
(V+ = 12V)
R
L
= 50
V+ = 3.3V
V+ = 12V
V+ = 12V
V+ = 3.3V
FREQUENCY (Hz)
1k 100k 1M 100M 500M10k 10M
110
10
20
30
40
50
60
70
80
90
100
OFF-ISOLATION (dB)
V+ = 3V to 13V
R
L
= 50
ISL84514, ISL84515
11
FN6025.5
June 9, 2014
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ISL84514, ISL84515
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
TOP VIEW
INDEX
AREA
123
-C-
SEATING PLANE
x 45°
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
SIDE VIEW “A
SIDE VIEW “B”
1.27 (0.050)
6.20 (0.244)
5.80 (0.228)
4.00 (0.157)
3.80 (0.150)
0.50 (0.20)
0.25 (0.01)
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
0.25(0.010)
0.10(0.004)
0.51(0.020)
0.33(0.013)
0.25 (0.010)
0.19 (0.008)
1.27 (0.050)
0.40 (0.016)
1.27 (0.050)
5.20(0.205)
1
2
3
4
5
6
7
8
TYPICAL RECOMMENDED LAND PATTERN
2.20 (0.087)
0.60 (0.023)
12
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June 9, 2014
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ISL84514, ISL84515
Package Outline Drawing
P5.064
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 3, 4/11
NOTES:
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
5x (1.2)
5x (0.60)
(2x 0.95)
(2.4)
SEE DETAIL X
3
3
(1.90)
0.10 (0.004) C
5
2
4
END VIEW
0.55
0.35
3.00
2.80
(1.90)
0.50
0.30
3.00
2.60
(0.95)
0.20 (0.008) CM
1.70
1.50
0.22
0.08
5
GAUGE PLANE
SEATING
C
PLANE
(0.60)
4
0.25
0.10
0.10 MIN
(0.25)
1.30
0.90
1.45
0.90
0.15
0.00
C
SEATING
PLANE
5
3
4
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC-74 and JEDEC MO178AA.
3. Package length and width are exclusive of mold flash, protrusions,
or gate burrs.
4. Footlength measured at reference to gauge plane.
5. Lead thickness applies to the flat section of the lead between
6. Controlling dimension: MILLIMETER.
0.08mm and 0.15mm from the lead tip.
Dimensions in ( ) for reference only.

ISL84515IHZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog Switch ICs SWITCH 1X SPST 3V-SS N C 5SOT INDEL
Lifecycle:
New from this manufacturer.
Delivery:
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