MC10EP101FAG Datasheet MC100EP101FAG, MC100EP101MNG, MC10EP101MNG | P1-P3

November, 2006 − Rev. 11

1 Publication Order Number:

MC10EP101/D

MC10EP101, MC100EP101

3.3V / 5VECL Quad 4−Input

OR/NOR

Description

The MC10/100EP101 is a Quad 4−input OR/NOR gate. The device

is functionally equivalent to the E101. With AC performance faster

than the E101 device, the EP101 is ideal for applications requiring the

fastest AC performance available.

The 100 Series contains temperature compensation.

Features

• 250 ps Typical Propagation Delay

• Maximum Frequency > 3 GHz Typical

• PECL Mode Operating Range: V

CC

= 3.0 V to 5.5 V

with V

EE

= 0 V

• NECL Mode Operating Range: V

CC

= 0 V

with V

EE

= −3.0 V to −5.5 V

• Open Input Default State

• Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

LQFP−32

FA SUFFIX

CASE 873A

MARKING

DIAGRAM*

*For additional marking information, refer to

Application Note AND8002/D.

http://onsemi.com

MCxxx

EP101

AWLYYWWG

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

ORDERING INFORMATION

xxx = 10 or 100

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G = Pb−Free Package

32

1

MCxxx

EP101

AWLYYWWG

G

1

QFN32

MN SUFFIX

CASE 488AM

(Note: Microdot may be in either location)

MC10EP101, MC100EP101

http://onsemi.com

2

NC

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

12345678

24 23 22 21 20 19 18 17

16

MC10EP101

MC100EP101

V

EE

D3d

D3c

V

CC

D3b

D3a

D2d

V

CC

V

CC

Q0

V

EE

D0a

D0b

D0c

V

CC

Q3Q3Q2Q2Q1V

CC

D2cD2bD2aD1dD1cD1bD0d D1a

Figure 1. 32−Lead LQFP Pinout (Top View)

Q1

Warning: All V

CC

and V

EE

pins must be externally connected to

Power Supply to guarantee proper operation.

Table 1. PIN DESCRIPTION

D0a*−D3d*

Q0−Q3, Q0−Q3 ECL Data Outputs

FUNCTION

ECL Data Inputs

V

CC

Positive Supply

V

EE

Negative Supply

D

0a

D

0b

D

0c

D

0d

D

1a

D

1b

D

1c

D

1d

D

2a

D

2b

D

2c

D

2d

D

3a

D

3b

D

3c

D

3d

Q

0

Q

0

Q

1

Q

1

Q

2

Q

2

Q

3

Q

3

Dna Dnb Dnc Dnd Qn Qn

LLLLLH

H XXX HL

XHXXHL

X XHX HL

X XXH HL

H HHH HL

Table 2. TRUTH TABLE

NC No Connect

V

EE

* Pins will default LOW when left open.

NC

2526272829303132

1514131211109

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

16

V

EE

D3d D3c V

CC

D3b D3a D2d

V

CC

V

CC

Q0 Q0 V

EE

D0a D0b D0c

V

CC

Q2

V

CC

D2c

D2b

D2a

D1d

D1c

D1b

D0d

D1a

Q1

Q2

Q3

Q1

MC10EP101

MC100EP101

Figure 2. 32−Lead QFN Pinout (Top View)

Figure 3. Logic Diagram

The Exposed Pad (EP) on the

QFN−32 package bottom is

thermally connected to the die

for improved heat transfer out

of package. The exposed pad

must be attached to a heat−

sinking conduit. The pad is

electrically connected to V

EE

.

EP for QFN−32,

only

MC10EP101, MC100EP101

http://onsemi.com

3

Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor

75 kW

Internal Input Pullup Resistor N/A

ESD Protection Human Body Model

Machine Model

Charged Device Model

> 4 kV

> 100 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg

LQFP−32

QFN−32

Level 2 Level 2

Level 1

Flammability Rating Oxygen Index: 28 to 34 UL−94 V−0 @ 0.125 in

Transistor Count 173 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

V

CC

PECL Mode Power Supply V

EE

= 0 V 6 V

V

EE

NECL Mode Power Supply V

CC

= 0 V −6 V

V

I

PECL Mode Input Voltage

NECL Mode Input Voltage

V

EE

= 0 V

V

CC

= 0 V

V

I

≤ V

CC

V

I

≤ V

EE

6

−6

V

I

out

Output Current Continuous

Surge

50

100

mA

I

BB

V

BB

Sink/Source ± 0.5 mA

T

A

Operating Temperature Range −40 to +85 °C

T

stg

Storage Temperature Range −65 to +150 °C

q

JA

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

32 LQFP

80

55

°C/W

q

JC

Thermal Resistance (Junction−to−Case) Standard 32 LQFP 12 to 17 °C/W

q

JA

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

QFN−32

31

27

°C/W

q

JC

Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W

T

sol

Wave Solder Pb

Pb−Free

265

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

MC10EP101FAG

MC10EP101FAG

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