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PCA9673DB,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
PCA9673 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 29 September 2011 4 of 33
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
6. Pinning information
6.1 Pinning
Fig 3. Pin configuration for SO24 Fig 4. Pin configuration for TSSOP24
Fig 5. Pin configuration for HVQFN24 Fig 6. Pin configuration for DHVQFN24
PCA9673D
INT V
DD
AD1 SDA
RESET SCL
P00 AD0
P01 P17
P02 P16
P03 P15
P04 P14
P05 P13
P06 P12
P07 P11
V
SS
P10
002aac301
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
V
DD
SDA
SCL
AD0
P17
P16
P15
P14
P13
P12
P11
P10
INT
AD1
P00
P01
P02
P03
P04
P05
P06
P07
V
SS
PCA9673PW
002aac302
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
RESET
V
DD
SDA
SCL
002aac305
PCA9673BS
Transparent top view
P13
P04
P05
P14
P03 P15
P02 P16
P01 P17
P00 AD0
P06
P07
P10
P11
P12
AD1
INT
terminal 1
index area
6
13
5
14
4 15
3 16
2 17
1
18
7
8
9
10
11
12
24
23
22
21
20
19
V
SS
RESET
INT
V
DD
AD1 SDA
RESET SCL
P00 AD0
P01 P17
P02 P16
P03 P15
P04 P14
P05 P13
P06 P12
P07 P11
V
SS
P10
002aac306
PCA9673BQ
Transparent top view
11 14
10 15
9 16
8 17
7 18
6 19
5 20
4 21
3 22
2 23
12
13
1
24
terminal 1
index area
PCA9673 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 29 September 2011 5 of 33
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
6.2 Pin description
[1] HVQFN24 and DHVQFN24 package die supply ground is connected to both the V
SS
pin and the exposed
center pad. The V
SS
pin must be connected to supply ground for proper device operation. For enhanced
thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
Table 2. Pin description
Symbol Pin Description
SO24, TSSOP24,
DHVQFN24
HVQFN24
INT
1 22 interrupt output (active LOW)
AD1 2 23 address input 1
RESET
3 24 reset input (active LOW)
P00 4 1 quasi-bidirectional I/O 00
P01 5 2 quasi-bidirectional I/O 01
P02 6 3 quasi-bidirectional I/O 02
P03 7 4 quasi-bidirectional I/O 03
P04 8 5 quasi-bidirectional I/O 04
P05 9 6 quasi-bidirectional I/O 05
P06 10 7 quasi-bidirectional I/O 06
P07 11 8 quasi-bidirectional I/O 07
V
SS
12
[1]
9
[1]
supply ground
P10 13 10 quasi-bidirectional I/O 10
P11 14 11 quasi-bidirectional I/O 11
P12 15 12 quasi-bidirectional I/O 12
P13 16 13 quasi-bidirectional I/O 13
P14 17 14 quasi-bidirectional I/O 14
P15 18 15 quasi-bidirectional I/O 15
P16 19 16 quasi-bidirectional I/O 16
P17 20 17 quasi-bidirectional I/O 17
AD0 21 18 address input 0
SCL 22 19 serial clock line input
SDA 23 20 serial data line input/output
V
DD
24 21 supply voltage
PCA9673 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 29 September 2011 6 of 33
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
7. Functional description
Refer to Figure 1 “Block diagram of PCA9673”.
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9673 is shown in Figure 7
. Slave address pins AD1 and AD0 choose 1 of 16 slave
addresses. To conserve power, no internal pull-up resistors are incorporated on AD1 and
AD0. Address values depending on AD1 and AD0 can be found in Table 3 “
PCA9673
address map”.
Remark: The General Call address (0000 0000b) and the Device ID address
(1111 100Xb) are reserved and cannot be used as device address. Failure to follow this
requirement will cause the PCA9673 not to acknowledge.
Remark: Reserved I
2
C-bus addresses must be used with caution since they can interfere
with:
• “reserved for future use” I
2
C-bus addresses (0000 011, 1111 101, 1111 110, 1111 111)
• slave devices that use the 10-bit addressing scheme (1111 0xx)
• High speed mode (Hs-mode) master code (0000 1xx)
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while a logic 0 selects a write operation.
When AD1 and AD0 are held to V
DD
or V
SS
, the same address as the PCF8575 is applied.
7.1.1 Address maps
Fig 7. PCA9673 address
Table 3. PCA9673 address map
AD1 AD0 A6 A5 A4 A3 A2 A1 A0 Address (hex)
SCL V
SS
001010028h
SCL V
DD
00101012Ah
SDA V
SS
00101102Ch
SDA V
DD
00101112Eh
SCLSCL001110038h
SCLSDA00111013Ah
SDASCL00111103Ch
SDASDA00111113Eh
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

PCA9673DB,118

Mfr. #:
Buy PCA9673DB,118
Manufacturer:
NXP Semiconductors
Description:
IC I/O EXPANDER I2C 16B 24SSOP
Lifecycle:
New from this manufacturer.
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