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74HC32N,652

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
1. General description
The 74HC32; 74HCT32 is a quad 2-input OR gate. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
V
CC
.
2. Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V
Complies with JEDEC standard JESD7A
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
Input levels:
For 74HC32: CMOS level
For 74HCT32: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
74HC32; 74HCT32
Quad 2-input OR gate
Rev. 5 — 4 September 2012 Product data sheet
74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 4 September 2012 2 of 17
NXP Semiconductors
74HC32; 74HCT32
Quad 2-input OR gate
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC32N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT32N
74HC32D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HCT32D
74HC32DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1
74HCT32DB
74HC32PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74HCT32PW
74HC32BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
SOT762-1
74HCT32BQ
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)
mna242
1A
1B
1Y
2
1
3
2A
2B
2Y
5
4
6
3A
3B
3Y
10
9
8
4A
4B
4Y
13
12
11
mna243
3
≥1
≥1
≥1
≥1
2
1
6
5
4
8
10
9
11
13
12
mna241
A
B
Y
74HC_HCT32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 4 September 2012 3 of 17
NXP Semiconductors
74HC32; 74HCT32
Quad 2-input OR gate
5. Pinning information
5.1 Pinning
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14
32
1A V
CC
1B 4B
1Y 4A
2A 4Y
2B 3B
2Y 3A
GND 3Y
001aad101
1
2
3
4
5
6
7 8
10
9
12
11
14
13
001aad102
32
Transparent top view
2Y 3A
2B 3B
2A 4Y
1Y 4A
4B1B
GND
(1)
GND
3Y
1A
V
CC
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
1A to 4A 1, 4, 9, 12 data input
1B to 4B 2, 5, 10,13 data input
1Y to 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
V
CC
14 supply voltage
Table 3. Function table
[1]
Input Output
nA nB nY
LLL
LHH
HLH
HHH
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

74HC32N,652

Mfr. #:
Buy 74HC32N,652
Manufacturer:
NXP Semiconductors
Description:
Logic Gates QUAD 2-IN OR GATE
Lifecycle:
New from this manufacturer.
Delivery:
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