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72V3631L20PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
4
COMMERCIAL TEMPERATURE RANGE
IDT72V3631/72V3641
3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)
(2)
Symbol Rating Commercial Unit
VCC Supply Voltage Range –0.5 to +4.6 V
V
I
(2)
Input Voltage Range –0.5 to VCC+0.5
(3)
V
V
O
(2)
Output Voltage Range –0.5 to VCC+0.5 V
IIK Input Clamp Current, (VI < 0 or VI > VCC) ±20 mA
I
OK Output Clamp Current, (VO = < 0 or VO > VCC) ±50 mA
I
OUT Continuous Output Current, (VO = 0 to VCC) ±50 mA
ICC Continuous Current Through VCC or GND ±400 mA
T
STG Storage Temperature Range –65 to 150 °C
IDT72V3631
IDT72V3641
Commercial
tCLK = 15 ns
Symbol Parameter Test Conditions Min. Typ.
(1)
Max. Unit
VOH Output Logic "1" Voltage VCC = 3.0V, IOH = –4 mA 2.4 — — V
VOL Output Logic "0" Voltage VCC = 3.0V, IOL = 8 mA — — 0.5 V
ILI Input Leakage Current (Any Input) VCC = 3.6V, VI = VCC or 0 — — ±5 μA
ILO Output Leakage Current VCC = 3.6V, VO = VCC or 0 — — ±5 μA
ICC2
(2)
Standby Current VCC = 3.6V, VI = VCC –0.2V or 0 — — 400 μA
CIN Input Capacitance VI = 0, f = 1 MHz — 4 — pF
COUT Output Capacitance VO = 0, f = 1 MHZ — 8 — pF
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25°C.
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
3. Control Inputs: maximum VI = 5.0V.
RECOMMENDED OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
V
CC Supply Voltage 3.0 3.3 3.6 V
VIH HIGH Level Input Voltage 2 — VCC+0.5 V
V
IL LOW-Level Input Voltage — — 0.8 V
IOH HIGH-Level Output Current — — –4 mA
IOL LOW-Level Output Current — — 8 mA
T
A Operating Free-air 0 — 70 °C
Temperature
5
COMMERCIAL TEMPERATURE RANGE
IDT72V3631/72V3641
3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT72V3641 with CLKA and CLKB set
to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize
the graph to a zero-capacitance load. Once the capacitance load per data-output channel and the number of IDT72V3631/72V3641 inputs driven by TTL HIGH
levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x ICC(f) + Σ(CL x VCC
2
x fO)
N
where:
N = number of outputs = 36
C
L = output capacitance load
f
O = switching frequency of an output
When no reads or writes are occurring on these devices, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is
calculated by:
P
T = VCC x fS x 0.025 mA/MHz
010203040506070
0
25
50
75
100
125
150
V
CC
= 3.3V
f
S
Clock Frequency MHz
I
CC(f)
Supply Current mA
f
data
= 1/2 f
S
T
A
= 25°C
C
L
= 0 pF
V
CC
= 3.0V
V
CC
= 3.6V
4658 drw 04
175
6
COMMERCIAL TEMPERATURE RANGE
IDT72V3631/72V3641
3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36
AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
IDT72V3631L15
IDT72V3641L15
Symbol Parameter Min. Max. Unit
fS Clock Frequency, CLKA or CLKB – 66.7 MHz
tCLK Clock Cycle Time, CLKA or CLKB 15 – ns
tCLKH Pulse Duration, CLKA or CLKB HIGH 6 – ns
tCLKL Pulse Duration, CLKA or CLKB LOW 6 – ns
tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑ 5–ns
tENS1 Setup Time, ENA to CLKA↑; ENB to CLKB↑ 5–ns
t
ENS2 Setup Time, CSA, W/RA, and MBA to CLKA↑; 7–ns
CSB, W/RB, and MBB to CLKB↑
tRMS Setup Time, RTM and RFM to CLKB↑ 6–ns
tRSTS Setup Time, RST LOW before CLKA↑ or CLKB↑
(1)
5–ns
tFSS Setup Time, FS0 and FS1 before RST HIGH 9 – ns
tSDS
(2)
Setup Time, FS0/SD before CLKA↑ 5–ns
tSENS
(2)
Setup Time, FS1/SEN before CLKA↑ 5–ns
tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 0.5 – ns
tENH1 Hold Time, ENA after CLKA↑; ENB after CLKB↑ 0.5 – ns
tENH2 Hold Time, CSA, W/RA, and MBA after CLKA↑; 0.5 – ns
CSB, W/RB, and MBB after CLKB↑
tRMH Hold Time, RTM and RFM after CLKB↑ 0.5 – ns
tRSTH Hold Time, RST LOW after CLKA↑ or CLKB↑
(1)
5–ns
tFSH Hold Time, FS0 and FS1 after RST HIGH 0 – ns
tSPH
(2)
Hold Time, FS1/SEN HIGH after RST HIGH 0 – ns
tSDH
(2)
Hold Time, FS0/SD after CLKA↑ 0–ns
tSENH
(2)
Hold Time, FS1/SEN after CLKA↑ 0–ns
tSKEW1
(3)
Skew Time, between CLKA↑ and CLKB↑ for OR and IR 9 – ns
tSKEW2
(3,4)
Skew Time, between CLKA↑ and CLKB↑ for AE and AF 12 – ns
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Only applies when serial load method is used to program flag Offset registers.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

72V3631L20PF8

Mfr. #:
Buy 72V3631L20PF8
Manufacturer:
IDT
Description:
FIFO 512 x 36 SyncFIFO, 3.3V
Lifecycle:
New from this manufacturer.
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