17
COMMERCIAL TEMPERATURE RANGE
IDT72V3631/72V3641
3.3V CMOS SYNCFIFO™ 512 x 36 and 1,024 x 36
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Figure 13. IR Timing from the End of Retransmit Mode when One or More Write Locations are Available
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. Depth is 512 for the IDT72V3631 and 1,024 for the IDT72V3641.
3. Y is the value loaded in the Almost-Full flag Offset register.
Figure 14.
AFAF
AFAF
AF
Timing from the End of Retransmit Mode when (Y+1) or More Write Locations are Available
Figure 15. Timing for Mail1 Register and
MBF1MBF1
MBF1MBF1
MBF1
Flag
t
SKEW1
CLKA
IR
CLKB
RTM
FIFO Filled to First Restransmit Word
1
2
One or More Write Locations Available
4658 drw 16
(1)
t
PIR
t
RMS
t
RMH
CLKA
AF
CLKB
RTM
tSKEW2
(Depth -Y) or More Words Past First Restransmit Word
1
2
(Y+1) or More Write Locations Available
4658 drw 17
(1)
tPAE
tRMS
tRMH
(2)
4658 drw 18
CLKA
ENA
A0 - A35
MBA
CSA
W/RA
CLKB
MBF1
CSB
MBB
ENB
B0 - B35
W/RB
W1
t
ENS2
t
ENH2
t
DS
t
DH
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS1
t
ENH1
t
DIS
W1 (Remains valid in Mail1 Register after read)
FIFO Output Register
t
ENS2
t
ENH2
t
ENS2
t
ENH2
t
ENS2
t
ENH2