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XC9572XL-7VQ64C

P1-P3P4-P6P7-P9P10-P10
DS057 (v2.0) April 3, 2007 www.xilinx.com 1
Product Specification
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• 5 ns pin-to-pin logic delays
• System frequency up to 178 MHz
• 72 macrocells with 1,600 usable gates
• Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (38 user I/O pins)
- 64-pin VQFP (52 user I/O pins)
- 100-pin TQFP (72 user I/O pins)
- Pb-free available for all packages
• Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
• Pin-compatible with 5V-core XC9572 device in the
44-pin PLCC package and the 100-pin TQFP package
WARNING: Programming temperature range of
T
A
= 0° C to +70° C
Description
The XC9572XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of four
54V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 5 ns. See Figure 2 for overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
CC
, the following equation may be
used:
I
CC
(mA) = MC
HS
(0.175*PT
HS
+ 0.345) + MC
LP
(0.052*PT
LP
+ 0.272) + 0.04 * MC
TOG
(MC
HS
+MC
LP
)* f
where:
MC
HS
= # macrocells in high-speed configuration
PT
HS
= average number of high-speed product terms
per macrocell
MC
LP
= # macrocells in low power configuration
PT
LP
= average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
CC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
0
XC9572XL High Performance
CPLD
DS057 (v2.0) April 3, 2007
00
Product Specification
R
XC9572XL High Performance CPLD
2 www.xilinx.com DS057 (v2.0) April 3, 2007
Product Specification
R
application note XAPP114, “Understanding XC9500XL
CPLD Power.”
Figure 1: Typical I
CC
vs. Frequency for XC9572XL
Clock Frequency (MHz)
Typical I
CC
(mA)
100 200
DS057_01_010102
125
100
25
50 150
75
50
0
104 MHz
High
P
erformance
178 MHz
Low Power
Figure 2: XC9572XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
54
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
DS057_02_082800
1
Function
Block 2
54
18
18
Function
Block 3
Macrocells
1 to 18
Macrocells
1 to 18
54
Function
Block 4
54
18
18
Fast CONNECT II Switch Matrix
XC9572XL High Performance CPLD
DS057 (v2.0) April 3, 2007 www.xilinx.com 3
Product Specification
R
Absolute Maximum Ratings
(2)
Recommended Operation Conditions
Quality and Reliability Characteristics
DC Characteristic Over Recommended Operating Conditions
Symbol Description Value Units
V
CC
Supply voltage relative to GND –0.5 to 4.0 V
V
IN
Input voltage relative to GND
(1)
–0.5 to 5.5 V
V
TS
Voltage applied to 3-state output
(1)
–0.5 to 5.5 V
T
STG
Storage temperature (ambient)
(3)
–65 to +150
o
C
T
J
Junction temperature +150
o
C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA. External I/O voltage may not exceed V
CCINT
by 4.0V.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free
packages, see XAPP427.
Symbol Parameter Min Max Units
V
CCINT
Supply voltage for internal logic
and input buffers
Commercial T
A
= 0
o
C to 70
o
C3.0 3.6 V
Industrial T
A
= –40
o
C to +85
o
C3.0 3.6 V
V
CCIO
Supply voltage for output drivers for 3.3V operation 3.0 3.6 V
Supply voltage for output drivers for 2.5V operation 2.3 2.7 V
V
IL
Low-level input voltage 0 0.80 V
V
IH
High-level input voltage 2.0 5.5 V
V
O
Output voltage 0 V
CCIO
V
Symbol Parameter Min Max Units
T
DR
Data Retention 20 - Years
N
PE
Program/Erase Cycles (Endurance) 10,000 - Cycles
V
ESD
Electrostatic Discharge (ESD) 2,000 - Volts
Symbol Parameter Test Conditions Min Max Units
V
OH
Output high voltage for 3.3V outputs I
OH
= –4.0 mA 2.4 - V
Output high voltage for 2.5V outputs I
OH
= –500 μA90% V
CCIO
-V
V
OL
Output low voltage for 3.3V outputs I
OL
= 8.0 mA - 0.4 V
Output low voltage for 2.5V outputs I
OL
= 500 μA-0.4V
I
IL
Input leakage current V
CC
= Max; V
IN
= GND or V
CC
-±10μA
I
IH
I/O high-Z leakage current V
CC
= Max; V
IN
= GND or V
CC
-±10μA
I
IH
I/O high-Z leakage current V
CC
= Max; V
CCIO
= Max;
V
IN
= GND or 3.6V
-±10μA
V
CC
Min < V
IN
< 5.5V - ±50 μA
C
IN
I/O capacitance V
IN
= GND; f = 1.0 MHz - 10 pF
I
CC
Operating supply current
(low power mode, active)
V
IN
= GND, No load; f = 1.0 MHz 20 (Typical) mA
P1-P3P4-P6P7-P9P10-P10

XC9572XL-7VQ64C

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Manufacturer:
Xilinx
Description:
CPLD - Complex Programmable Logic Devices 3.3V 72-mc CPLD
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