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DM74S280N

P1-P3P4-P5
© 2000 Fairchild Semiconductor Corporation DS006483 www.fairchildsemi.com
August 1986
Revised May 2000
DM74S280 9-Bit Parity Generator/Checker
DM74S280
9-Bit Parity Generator/Checker
General Description
These universal, nine-bit parity generators/checkers utilize
Schottky-clamped TTL high-performance circuitry, and fea-
ture odd/even outputs to facilitate operation of either odd or
even parity applications. The word-length capability is eas-
ily expanded by cascading.
The DM74S280 can be used to upgrade the performance
of most systems utilizing the DM74180 parity generator/
checker. Although the DM74S280 is implemented without
expander inputs, the corresponding function is provided by
the availability of all input at pin 4, and no internal connec-
tion at pin 3. This permits the DM74S280 to be substituted
for the 180 in existing designs to produce an identical func-
tion, even if DM74S280’s are mixed with existing 180’s.
Input buffers are provided so that each input represents
only one normal 74S load, and full fan-out to 10 normal
Series 74S loads is available from each of the outputs at
low logic levels. A fan-out to 20 normal Series 74S loads is
provided at high logic levels, to facilitate connection of
unused inputs to used inputs.
Features
■ Generates either odd or even parity for nine data lines
■ Cascadable for N-bits
■ Can be used to upgrade existing systems using MSI par-
ity circuits
■ Typical data-to-output delay—14 ns
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
Order Number Package Number Package Description
DM74S280M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74S280N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Number of Inputs Outputs
(A Thru I) that are HIGH ∑ Even ∑ Odd
0, 2, 4, 6, 8 H L
1, 3, 5, 7, 9 L H
www.fairchildsemi.com 2
DM74S280
Logic Diagram
Typical Applications
Three DM74S280’s can be used to implement a 25-line
parity generator/checker. This arrangement will provide
parity in typically 25 ns. (See Figure 1.)
Longer word lengths can be implemented by cascading
DM74S280’s. As shown in Figure 2, parity can be gener-
ated for word lengths up to 81 bits in typically 25 ns.
FIGURE 1. 25-Line Parity/Generator Checker
FIGURE 2. 81-Line Parity/Generator Checker
3 www.fairchildsemi.com
DM74S280
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 2: All typicals are at V
CC
= 5V, T
A
= 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4: I
CC
is measured with all inputs grounded and all outputs OPEN.
Switching Characteristics
at V
CC
= 5V and T
A
= 25°C
Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Symbol Parameter Min Nom Max Units
V
CC
Supply Voltage 4.75 5 5.25 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current −1mA
I
OL
LOW Level Output Current 20 mA
T
A
Free Air Operating Temperature 0 70 °C
Symbol Parameter Conditions Min
Typ
Max Units
(Note 2)
V
I
Input Clamp Voltage V
CC
= Min, I
I
=−18 mA −1.2 V
V
OH
HIGH Level V
CC
= Min, I
OH
= Max
2.7 3.4 V
Output Voltage V
IL
= Max, V
IH
= Min
V
OL
LOW Level V
CC
= Min, I
OL
=Max
0.5 V
Output Voltage V
IH
= Min, V
IL
= Max
I
I
Input Current @ Max Input Voltage V
CC
= Max, V
I
= 5.5V 1 mA
I
IH
HIGH Level Input Current V
CC
= Max, V
I
= 2.7V 50 µA
I
IL
LOW Level Input Current V
CC
= Max, V
I
= 0.5V −2mA
I
OS
Short Circuit Output Current V
CC
= Max (Note 3) −40 −100 mA
I
CC
Supply Current V
CC
Max (Note 4) 67 105 mA
R
L
= 280Ω R
L
= 280Ω
Symbol Parameter
From (Input)
C
L
= 15 pF C
L
= 50 pF Units
To (Output) Min Max Min Max
t
PLH
Propagation Delay Time
Data to ∑ Even 21 24 ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Data to ∑ Even 18 21 ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Data to ∑ Odd 21 24 ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Data to ∑ Odd 18 21 ns
HIGH-to-LOW Level Output
P1-P3P4-P5

DM74S280N

Mfr. #:
Buy DM74S280N
Manufacturer:
ON Semiconductor / Fairchild
Description:
Parity Functions 9-Bit Par Gen/Check
Lifecycle:
New from this manufacturer.
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