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CS5566-ISZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
CS5566
DS806PP1 13
3/25/08
2. OVERVIEW
The CS5566 is a 24-bit analog-to-digital converter capable of 5 kSps conversion rate. The device is ca-
pable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a
low-latency digital filter architecture. The filter is designed for fast settling and settles to full accuracy in
one conversion.
The converter is a serial output device. The serial port can be configured to function as either a master or
a slave.
The converter can operate from an analog supply of 5V or from ±2.5V. The digital interface supports stan-
dard logic operating from 1.8, 2.5, or 3.3 V.
The CS5566 converts at 5 kSps when operating from a 8 MHz input clock.
3. THEORY OF OPERATION
The CS5566 converter provides high-performance measurement of DC or AC signals. The converter can
be used to perform single conversions or continuous conversions upon command. Each conversion is in-
dependent of previous conversions and can settle to full specified accuracy, even with a full-scale input
voltage step. This is due to the converter architecture which uses a combination of a high-speed delta-sig-
ma modulator and a low-latency filter architecture.
Once power is established to the converter, a reset must be performed. A reset initializes the internal con-
verter logic.
If CONV
is held low then the converter will convert continuously with RDY falling every 1600 MCLKs. This
is equivalent to 5 kSps if MCLK = 8.0 MHz. If CONV
is tied to RDY, a conversion will occur every
1602 MCLKs. If CONV
is operated asynchronously to MCLK, it may take up to 1604 MCLKs from CONV
falling to RDY falling.
Multiple converters can operate synchronously if they are driven by the same MCLK source and CONV
to each converter falls on the same MCLK falling edge. Alternately, CONV can be held low and all devices
are reset with RST
rising on the same falling edge of MCLK.
The output coding of the conversion word is a function of the BP/UP
pin.
The active-low SLEEP
signal causes the device to enter a low-power state. When exiting sleep, the con-
verter will take 3083 MCLK cycles before conversions can be performed. RST
should remain inactive
(high) when SLEEP
is asserted (low).
CS5566
14 DS806PP1
3/25/08
3.1 Converter Operation
The converter should be reset after the power supplies and voltage reference are stable.
The CS5566 converts at 5 kSps when synchronously operated (CONV
= VLR) from a 8.0 MHz master
clock. Conversion is initiated by taking CONV
low. A conversion lasts 1600 master clock cycles, but if
CONV
is asynchronous to MCLK there may be an uncertainty of 0-4 MCLK cycles after CONV falls to
when a conversion actually begins. This may extend the throughput to 1604 MCLKs
When the conversion is completed, the output word is placed into the serial port and RDY
goes low. To
convert continuously, CONV
should be held low. In continuous conversion mode with CONV held low, a
conversion is performed in 1600 MCLK cycles. Alternately RDY
can be tied to CONV and a conversion
will occur every 1602 MCLK cycles.
To perform only one conversion, CONV
should return high at least 20 master clock cycles before RDY
falls.
Once a conversion is completed and RDY
falls, RDY will return high when all the bits of the data word are
emptied from the serial port or if the conversion data is not read and CS
is held low, RDY will go high two
MCLK cycles before the end of conversion. RDY
will fall at the end of the next conversion when new data
is put into the port register.
See Section 3.11 Serial Port for information about reading conversion data.
Conversion performance can be affected by several factors. These include the choice of clock source for
the chip, the timing of CONV
, and the choice of the serial port mode.
The converter can be operated from an internal oscillator. This clock source has greater jitter than an ex-
ternal crystal-based clock. Jitter may not be an issue when measuring DC signals, or very-low-frequency
AC signals, but can become an issue for higher frequency AC signals. For maximum performance when
digitizing AC signals, a low-jitter MCLK should be used.
To maximize performance, the CONV
pin should be held low in the continuous conversion state to per-
form multiple conversions, or CONV
should occur synchronous to MCLK, falling when MCLK falls.
If the converter is operated at maximum throughput, the SSC serial port mode is less likely to cause in-
terference to measurements as the SCLK output is synchronized to the MCLK. Alternately, any interfer-
ence due to serial port clocking can also be minimized if data is read in the SEC serial port mode when a
conversion is not in progress.
CS5566
DS806PP1 15
3/25/08
3.2 Power Consumption
The power consumption of the CS5566 converter is a function of the conversion rate. Figure 6 illustrates
the typical power consumption of the converter when operating from either MCLK = 8 MHz or
MCLK = 4 MHz. The rate at which conversions are performed directly affects the power consumption.
When the converter is powered but not converting, it is in an idle state where its power consumption is
about 11 mW. When the CONV
signal goes low to start a conversion, the converter delays the actual start
of conversion for 1182 to 1186 MCLK cycles, depending upon how CONV
is controlled. The timing for the
conversion sequence is shown in Figure 1 on page 6. After the 1182 - 1186 MCLK delay from when
CONV
goes low, the converter enters a higher-power state for 354 MCLK cycles and then returns to a
lower-power state for 64 MCLK cycles, after which the RDY
signal falls to indicate the completion of a
conversion. Since the peak operating current for the converter occurs during the 354 MCLK, higher-pow-
er state, it is recommended that a large capacitor be used on the supply to the converter (as shown in
Figures 9 and 10). This capacitor filters the peak current demand from the power supply. The average
power consumption for the converter will depend upon the frequency of MCLK and the rate at which con-
versions are performed as illustrated in Figure 1 on page 6.
Figure 6. Power Consumption vs. Conversion Rate
7.5
10
12.5
15
17.5
20
0 5001k 1.5 2k2.5k3k3.5k4k4.5k5k
Word Rate (Sps )
Power Consumption (mW)
MCLK = 8MHz
MCLK = 4MHz
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CS5566-ISZ

Mfr. #:
Buy CS5566-ISZ
Manufacturer:
Cirrus Logic
Description:
Analog to Digital Converters - ADC 24-Bit 5 kSps ADC
Lifecycle:
New from this manufacturer.
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