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CS5566-ISZR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
CS5566
4 DS806PP1
3/25/08
1. CHARACTERISTICS AND SPECIFICATIONS
• Min / Max characteristics and specifications are guaranteed over the specified operating conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and T
A
= 25°C.
• VLR = 0 V. All voltages with respect to 0 V.
ANALOG CHARACTERISTICS T
A
= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V,
±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 8 MHz; SMODE = VL. BUFEN = V1+
unless otherwise stated. Connected per Figure 8. Bipolar mode unless otherwise stated.
1. No missing codes is guaranteed at 24 bits resolution over the specified temperature range.
2. One LSB is equivalent to (2 x VREF) ÷ 2
24
or (2 x 4.096) ÷ 16,777,216 = 488 nV.
3. Scales with MCLK.
4. Measured using an input signal of 1 V DC.
Parameter Min Typ Max Unit
Accuracy
Linearity Error - 0.0005 - ±%FS
Differential Linearity Error (Note 1) - ±0.1 - LSB
24
Positive Full-scale Error - 1.0 - %FS
Negative Full-scale Error - 1.0 - %FS
Full-scale Drift (Note 2) - 1 - PPM / °C
Bipolar Offset (Note 2) - ±500 - LSB
24
Bipolar Offset Drift (Note 2) - 1 - LSB / °C
Noise - 9.5 - µVrms
Dynamic Performance
Peak Harmonic or Spurious Noise 200 Hz, -0.5 dB Input - -115 - dB
Total Harmonic Distortion 200 Hz, -0.5 dB Input - -110 -100 dB
Signal-to-Noise 108 110 - dB
S/(N + D) Ratio -0.5 dB Input, 200 Hz
-60 dB Input, 200 Hz
-
-
109
50
-
-
dB
dB
-3 dB Input Bandwidth (Note 3) - 21 - kHz
Analog Input
Analog Input Range (Differential) Unipolar
Bipolar
0 to +VREF
±VREF
V
V
Input Capacitance - 10 - pF
CVF Current (Note 4) AIN Buffer On (BUFEN = V+)
AIN Buffer Off (BUFEN = V-)
-
-
600
130
-
-
nA
µA
Common Mode Rejection Ratio (DC to 2 kHz) -100 -110 - dB
CS5566
DS806PP1 5
3/25/08
ANALOG CHARACTERISTICS (CONTINUED) T
A
= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- =
V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 8 MHz; SMODE = VL.;
BUFEN = V1+ unless otherwise stated. Connected per Figure 8.
5. For optimum performance, VREF+ should always be less than (V+) - 0.2 volts to prevent saturation of the VREF+ input buffer.
6. Specification is for MCLK = 8MHz and 5 kSps conversion rate. MCLK frequency and conversion rate affect power consumption.
See Section 3.2 Power Consumption for more details.
7. Tested with 100 mVP-P on any supply up to 2 kHz. V1+ and V2+ supplies at the same voltage potential, V1- and V2- supplies at
the same voltage potential.
Parameter Min Typ Max Unit
Voltage Reference Input
Voltage Reference Input Range
(VREF+) – (VREF-) (Note 5) 2.4 4.096
4.2
V
Input Capacitance - 10 - pF
CVF Current VREF+ Buffer On (BUFEN = V+)
VREF+ Buffer Off (BUFEN = V-)
VREF-
-
-
-
3
1
1
-
-
-
µA
mA
mA
Power Supplies
Average DC Power Supply Currents (Note 6) I
V1
I
V2
I
VL
-
-
-
-
-
-
5
0.6
0.4
mA
mA
mA
Peak DC Power Supply Currents (Note 6) I
V1
I
V2
I
VL
-
-
-
-
-
-
9
1.2
280
mA
mA
µA
Average Power Consumption Normal Operation Buffers On
(Note 6) Buffers Off
Sleep (SLEEP = 0)
-
-
-
20
15
6
-
-
-
mW
mW
mW
Power Supply Rejection (Note 7) V1+ , V2+ Supplies
V1-, V2- Supplies
75
75
85
85
-
-
dB
dB
CS5566
6 DS806PP1
3/25/08
SWITCHING CHARACTERISTICS
T
A
= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF.
8. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.
9. If CONV
is held low continuously, conversions occur every 1600 MCLK cycles.
If RDY is tied to CONV, conversions will occur every 1602 MCLKs.
If CONV is operated asynchronously to MCLK, a conversion may take up to 1604 MCLKs.
RDY falls at the end of conversion.
10. RDY
will fall when the device is fully operational when coming out of sleep mode.
Figure 1. Converter Status (Not to scale)
Parameter Symbol Min Typ Max Unit
Master Clock Frequency Internal Oscillator
External Clock
XIN
f
clk
6
0.5
7
8
8
8.1
MHz
MHz
Master Clock Duty Cycle 40 - 60 %
Reset
RST
Low Time t
res
1--µs
RST
rising to RDY falling Internal Oscillator
External Clock
t
wup
-
-
240
3084
-
-
µs
MCLKs
Conversion
CONV
Pulse Width t
cpw
4--MCLKs
BP/UP
setup to CONV falling (Note 8) t
scn
0--ns
CONV
low to start of conversion t
scn
- 1182 1186 MCLKs
Perform Single Conversion (CONV
high before RDY falling) t
bus
20 - - MCLKs
Conversion Time (Note 9)
Start of Conversion to RDY
falling t
buh
- - 1604 MCLKs
Sleep Mode
SLEEP
low to low-power state
SLEEP
high to device active (Note 10)
t
con
t
con
-
-
50
3083
-
-
µs
MCLKs
1182 - 1186 MCLKs
Converter
Status
CONVERT
RDY
IDLEIDLE CONVERT
SDO
ACTIVE
t
bus
354 + 64 MCLKs
1600 - 1604 MCLKs
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

CS5566-ISZR

Mfr. #:
Buy CS5566-ISZR
Manufacturer:
Cirrus Logic
Description:
Analog to Digital Converters - ADC IC ADC DELTA-SIGMA 24-SSOP 24b/5kSPS
Lifecycle:
New from this manufacturer.
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