6
Figure 2: Waveforms for Positive Clock Edge Related Delays
Figure 1. Reset Waveform
Switching Characteristics
Table 5. Switching Characteristics Max/Min specifications at V
DD
= 5.0 ± 5%, T
A
= -40 to +85
O
C, C
L
= 40 pf
Symbol Description Min. Max. Units
1 tCLK Clock Period 70 ns
2 tCHH Pulse width, clock high 28 ns
3 tCD Delay time, rising edge of clock to valid, updated count information on
D0-7
65 ns
4 tODE Delay time, OE fall to valid data 65 ns
5 tODZ Delay time, OE rise to Hi-Z state on D0-7 40 ns
6 tSDV Delay time, SEL valid to stable, selected data byte (delay to High Byte
= delay to Low Byte)
65 ns
7 tCLH Pulse width, clock low 28 ns
8 tSS Setup time, SEL before clock fall 20 ns
9 tOS Setup time, OEN before clock fall 20 ns
10 tSH Hold time, SEL after clock fall 0 ns
11 tOH Hold time, OE after clock fall 0 ns
12 tRST Pulse width, RST low 28 ns
13 tDCD Hold time, last position count stable on D0-7 after clock rise 10 ns
14 tDSD Hold time, last data byte stable after next SEL state change 10 ns
15 tDOD Hold time, data byte stable after OE rise 10 ns
16 tUDD Delay time, U/D valid after clock rise 45 ns
17 tCHD Delay time, CNTDCDR or CNTCAS high after clock rise 45 ns
18 tCLD Delay time, CNTDCDRor CNTCAS low after clock fall 45 ns
19 tUDH Hold time, U/D stable after clock rise 10 ns
20 tUDCS Setup time, U/D valid before CNTDCDR or CNTCAS rise tCLK-45 ns
21 tUDCH Hold time, U/D stable after CNTDCDR or CNTCAS rise tCLK-45 ns
