DS1302 Trickle-Charge Timekeeping Chip
7 of 13
CLOCK HALT FLAG
Bit 7 of the seconds register is defined as the clock halt (CH) flag. When this bit is set to logic 1, the clock oscillator
is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less than 100nA. When
this bit is written to logic 0, the clock will start. The initial power-on state is not defined.
WRITE-PROTECT BIT
Bit 7 of the control register is the write-protect bit. The first seven bits (bits 0 to 6) are forced to 0 and always read 0
when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high, the write-protect bit
prevents a write operation to any other register. The initial power-on state is not defined. Therefore, the WP bit
should be cleared before attempting to write to the device.
TRICKLE-CHARGE REGISTER
This register controls the trickle-charge characteristics of the DS1302. The simplified schematic of Figure 5 shows
the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of
the trickle charger. To prevent accidental enabling, only a pattern of 1010 enables the trickle charger. All other
patterns will disable the trickle charger. The DS1302 powers up with the trickle charger disabled. The diode select
(DS) bits (bits 2 and 3) select whether one diode or two diodes are connected between V
CC2
and V
CC1
. If DS is 01,
one diode is selected or if DS is 10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled
independently of TCS. The RS bits (bits 0 and 1) select the resistor that is connected between V
CC2
and V
CC1
. The
resistor and diodes are selected by the RS and DS bits as shown in Table 2.
Table 2. Trickle Charger Resistor and Diode Select
TCS
BIT 7
TCS
BIT 6
TCS
BIT 5
TCS
BIT 4
DS
BIT 3
DS
BIT 2
RS
BIT 1
RS
BIT 0
FUNCTION
X X X X X X 0 0 Disabled
X X X X 0 0 X X Disabled
X X X X 1 1 X X Disabled
1 0 1 0 0 1 0 1
1 Diode, 2kΩ
1 0 1 0 0 1 1 0
1 Diode, 4kΩ
1 0 1 0 0 1 1 1
1 Diode, 8kΩ
1 0 1 0 1 0 0 1
2 Diodes, 2kΩ
1 0 1 0 1 0 1 0
2 Diodes, 4kΩ
1 0 1 0 1 0 1 1
2 Diodes, 8kΩ
0 1 0 1 1 1 0 0 Initial power-on state
Diode and resistor selection is determined by the user according to the maximum current
desired for battery or
super cap charging. The maximum charging current can be calculated as illustrated in the following example.
Assume that a system power supply of 5V is applied to V
CC2
and a super cap is connected to V
CC1
. Also assume
that the trickle charger has been enabled with one diode and resistor R1 between V
CC2
and V
CC1
. The maximum
current I
MAX
would therefore be calculated as follows:
I
MAX
= (5.0V – diode drop) / R1 (5.0V – 0.7V) / 2kΩ 2.2mA
As the super cap charges, the voltage drop between V
CC2
and V
CC1
decreases and therefore the charge current
decreases.
DS1302 Trickle-Charge Timekeeping Chip
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CLOCK/CALENDAR BURST MODE
The clock/calendar command byte specifies burst mode operation. In this mode, the first eight clock/calendar
registers can be consecutively read or written (see Table 3) starting with bit 0 of address 0.
If the write-protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to
any of the
eight clock/calendar regi
sters (this includes the control register). The trickle charger is not accessible in
burst mode.
At the beginning of a clock burst read, the current time is transferred to a secon
d set of registers. The time
information is read from these secondary registers, while the clock may continue to run. This eliminates the need to
re-read the registers in case of an update of the main registers during a read.
RAM
The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space.
RAM BURST MODE
The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively
read or written (see Table 3) starting with bit 0 of address 0.
REGISTER SUMMARY
A register data format summary is shown in Table 3.
CRYSTAL SELECTION
A 32.768kHz crystal can be directly connected to the DS1302 via pins 2 and 3 (X1, X2). The crystal selected for
use should have a specified load capacitance (C
L
) of 6pF. For more information on crystal selection and crystal
layout consideration, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks.
Figure 4. Data Transfer Summary
A1 A2 A3 A4 R/C
1
CE
SCLK
I/O
R/W A0
D1 D2 D3 D4 D5 D6
D7D0
SINGLE-BYTE READ
A1 A2 A3 A4 R/C 1
CE
SCLK
I/O
R/W
A0 D1 D2 D3 D4 D5 D6 D7D0
SINGLE-BYTE WRITE
NOTE: IN BURST MODE, CE IS KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE END OF THE BURST.
DS1302 Trickle-Charge Timekeeping Chip
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Table 3. Register Address/Definition
RTC
READ WRITE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RANGE
81h 80h CH 10 Seconds Seconds 00–59
83h 82h 10 Minutes Minutes 00–59
10
85h 84h
12/
24
0
AM/PM
Hour Hour 1–12/0–23
87h 86h 0 0 10 Date Date 1–31
89h 88h 0 0 0
10
Month
Month 1–12
8Bh 8Ah 0 0 0 0 0 Day 1–7
8Dh 8Ch 10 Year Year 00–99
8Fh 8Eh WP 0 0 0 0 0 0 0
91h 90h TCS TCS TCS TCS DS DS RS RS
CLOCK BURST
BFh BEh
RAM
C1h C0h 00-FFh
C3h C2h 00-FFh
C5h C4h 00-FFh
.
.
.
.
.
.
.
.
.
FDh FCh 00-FFh
RAM BURST
FFh FEh
Figure 5. Programmable Trickle Charger
2K
Ω
4k
Ω
8k
Ω
R1
R3
R2
V
CC2
V
CC1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0
TRICKLE CHARGE REGISTER (90h write, 91h read)
1 0F 16 SELECT
NOTE: ONLY 1010b ENABLES CHARGER
1 OF 2
SELECT
1 OF 3
SELECT
TCS
0-3
= TRICKLE CHARGER SELECT
DS
0-1
= DIODE SELECT
ROUT
0-1
= RESISTOR SELECT

DS1302N

Mfr. #:
Manufacturer:
Description:
Real Time Clock Trickle-Charge Timekeeping Chip
Lifecycle:
New from this manufacturer.
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