6.42
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
11
IDT70P264/254/244L Datasheet
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
(1,5,8)
NOTES:
1. R/W or CE or UB & LB must be high during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of a low UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. t
WR is measured from the earlier of CE or R/W going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
WP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required t
DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified
t
WP.
9. To access SRAM, CE = V
IL, UB or LB = VIL.
R/W
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4) (4)
(7)
7148 drw 06
CE
(7)
(3)
CE
(9)
(9)
(9)
ADDRESS
t
AW
CE
t
WC
7148 drw 07
t
AS
t
WR
t
DW
t
DH
DATA
IN
R/W
t
EW
UB or LB
(9)
(3)
(2)
(6)
,
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing
(1,5)
