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AD5557CRU

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Data Sheet AD5547/AD5557
Rev. D | Page 7 of 20
Pin No. Mnemonic Function
19 A0 Address Pin 0. Signal level must be ≤V
DD
+ 0.3 V.
20 A1 Address Pin 1. Signal level must be ≤V
DD
+ 0.3 V.
21 LDAC Digital Input Load DAC Control. Signal level must be ≤V
DD
+ 0.3 V.
22 MSB Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The
signal level must be ≤V
DD
+ 0.3 V.
23
RS
Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1.
Signal level must be ≤V
DD
+ 0.3 V.
29 VDD Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.
AD5547/AD5557 Data Sheet
Rev. D | Page 8 of 20
NC
1
NC
2
R
OFSA
3
R
FBA
4
R
1A
5
V
REFA
7
I
OUTA
8
AGNDA
9
DGND
10
AGNDB
11
I
OUTB
12
V
REFB
13
R
COMB
14
R
1B
15
R
FBB
16
R
OFSB
17
18
A0
19
R
COMA
6
WR
NC = NO CONNECT
D0
38
D1
37
D2
36
D3
35
D4
34
D5
33
D6
32
D7
31
D8
30
VDD
29
D9
28
D10
27
D11
26
D12
25
D13
24
23
MSB
22
LDAC
21
A1
20
RS
04452-004
AD5557
TOP VIEW
(Not to Scale)
Figure 5. AD5557 Pin Configuration
Table 4. AD5557 Pin Function Descriptions
Pin No. Mnemonic Function
1, 2 NC No Connection. Do not connect anything other than the dummy pads to these pins.
3 R
OFSA
Bipolar Offset Resistor A. Accepts up to ±18 V. In 2-quadrant mode, R
OFSA
ties to R
FBA
. In 4-quadrant mode, R
OFSA
ties to R
1A
and the external reference.
4 R
FBA
Internal Matching Feedback Resistor A. Connects to the external op amp for I-to-V conversion.
5 R
1A
4-Quandrant Resistor. In 2-quadrant mode, R
1A
shorts to the V
RE FA
pin. In 4-quadrant mode, R
1A
ties to R
OFSA
. Do
not connect when operating in unipolar mode.
6 R
COMA
Center Tap Point of the Two 4-Quadrant Resistors, R
1A
and R
2A
. In 4-quadrant mode, R
COMA
ties to the inverting
node of the reference amplifier. In 2-quadrant mode, R
COMA
shorts to the V
REFA
pin. Do not connect if operating
in unipolar mode.
7 V
REFA
DAC A Reference Input in 2-Quadrant Mode, R2 Terminal in 4-Quadrant Mode. In 2-quadrant mode, V
RE FA
is the
reference input with constant input resistance vs. code. In 4-quadrant mode, V
RE FA
is driven by the external
reference amplifier.
8 I
OUTA
DAC A Current Output. Connects to the inverting terminal of external precision I-to-V op amp for voltage
output.
9 AGNDA DAC A Analog Ground.
10 DGND Digital Ground.
11 AGNDB DAC B Analog Ground.
12 I
OUTB
DAC B Current Output. Connects to inverting terminal of external precision I-to-V op amp for voltage output.
13 V
REFB
DAC B Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code. If configured
with an external op amp for 4-quadrant multiplying, V
REFB
becomes –V
REF
.
14 R
COMB
Center Tap Point of the Two 4-Quadrant Resistors, R
1B
and R
2B
. In 4-quadrant mode, R
COMB
ties to the inverting
node of the reference amplifier. In 2-quadrant mode, R
COMB
shorts to the V
REFB
pin. Do not connect if operating
in unipolar mode.
15 R
1B
4-Quandrant Resistor. In 2-quadrant mode, R
1B
shorts to the V
REFB
pin. In 4-quadrant mode, R
1B
ties to R
OFSB
. Do
not connect if operating in unipolar mode.
16 R
FBB
Internal Matching Feedback Resistor B. Connects to external op amp for I-to-V conversion.
17 R
OFSB
Bipolar Offset Resistor B. Accepts up to ±18 V. In 2-quadrant mode, R
OFSB
ties to R
FBB
. In 4-quadrant mode, R
OFSB
ties to R
1B
and an external reference.
18
WR
Write Control Digital Input In, Active Low. Transfers shift register data to the DAC register on the rising edge.
Signal level must be ≤V
DD
+ 0.3 V.
19 A0 Address Pin 0. Signal level must be ≤V
DD
+ 0.3 V.
20 A1 Address Pin 1. Signal level must be ≤V
DD
+ 0.3 V.
21 LDAC Digital Input Load DAC Control. Signal level must be ≤V
DD
+ 0.3 V.
22 MSB Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The
signal level must be ≤V
DD
+ 0.3 V.
Data Sheet AD5547/AD5557
Rev. D | Page 9 of 20
Pin No. Mnemonic Function
23
RS
Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1.
Signal level must be ≤V
DD
+ 0.3 V.
24 to 28,
30 to 38
D13 to D0 Digital Input Data Bits D13 to D0. Signal level must be ≤V
DD
+ 0.3 V.
29
VDD
Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.
Table 5. Address Decoder Pins
A1 A0 Output Update
0 0 DAC A
0 1 None
1 0 DAC A and DAC B
1 1 DAC B
Table 6. Control Inputs
RS
WR
LDAC Register Operation
0
X
X
Reset the output to 0 with MSB = 0; reset the output to midscale with MSB = 1.
1 0 0 Load the input register with data bits.
1 1 1 Load the DAC register with the contents of the input register.
1 0 1 The input and DAC registers are transparent.
1
When LDAC and
WR
are tied toge
ther and programmed as a pulse, the data bits are loaded into the input register
on the falling edge of the pulse and are then loaded into the DAC register on the rising edge of the pulse.
1 1 0 No register operation.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD5557CRU

Mfr. #:
Buy AD5557CRU
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Dual 14 bit parallel I-out output IC
Lifecycle:
New from this manufacturer.
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