OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ADM8321WCY46ARJZR7

P1-P3P4-P6P7-P9P10-P12P13-P15
ADM8316/ADM8318/ADM8319/ADM8320/ADM8321/ADM8322 Data Sheet
Rev. B | Page 10 of 15
THEORY OF OPERATION
CIRCUIT DESCRIPTION
The ADM8316/ADM8318/ADM8319/ADM8320/ADM8321/
ADM8322 provide microprocessor supply voltage supervision
by controlling the microprocessor reset input. Code execution
errors are avoided during power-up, power-down, and brownout
conditions by asserting a reset signal when the supply voltage
is below a preset threshold and by allowing supply voltage
stabilization with a fixed timeout reset delay after the supply
voltage rises above the threshold. In addition, problems with
microprocessor code execution can be monitored and corrected
with a watchdog timer (ADM8316/ADM8318/ADM8320/
ADM8321). If the user detects a problem with system operation, a
manual reset input is available (ADM8316/ADM8319/ADM8320/
ADM8322) to reset the microprocessor, for example, by means
of an external push-button switch.
PUSH-PULL RESET OUTPUT
The ADM8316 features an active low push-pull reset output,
whereas the ADM8321/ADM8322 have active high push-pull
reset outputs. The ADM8318/ADM8319 feature dual active low
and active high push-pull reset outputs. For active low and active
high outputs, the reset signal is guaranteed to be valid for V
CC
down to 0.9 V.
The reset output is asserted when V
CC
is below the reset threshold
(V
TH
), when
MR
is driven low, or when WDI is not serviced
within the watchdog timeout period (t
WD
). The reset output
remains asserted for the duration of the reset active timeout
period (t
RP
) after V
CC
rises above the reset threshold, after
MR
transitions from low to high, or after the watchdog timer times
out. Figure 20 illustrates the behavior of the reset outputs.
Figure 20. Reset Timing Diagram
OPEN-DRAIN RESET OUTPUT
The ADM8320/ADM8321/ADM8322 have an active low, open-
drain reset output. This output structure requires an external
pull-up resistor to connect the reset output to a voltage rail no
higher than V
CC
. A resistor that complies with the logic low and
logic high voltage level requirements of the microprocessor
while supplying input current and leakage paths on the
RESET
line is recommended. A 10 kΩ resistor is adequate in most
situations.
MANUAL RESET INPUT
The ADM8316/ADM8319/ADM8320/ADM8322 feature a manual
reset input (
MR
), which when driven low, asserts the reset output.
When
MR
transitions from low to high, the reset remains asserted
for the duration of the reset active timeout period before
deasserting. The
MR
input has a 75 kΩ, internal pull-up resistor
so that the input is always high when unconnected. An external
push-button switch can be connected between
MR
and ground
so that the user can generate a reset. Debounce circuitry for this
purpose is integrated on chip. Noise immunity is provided on the
MR
input, and fast, negative going transients of up to 100 ns
(typical) are ignored. A 0.1 μF capacitor between
MR
and ground
provides additional noise immunity.
WATCHDOG INPUT
The ADM8316/ADM8318/ADM8320/ADM8321 feature a
watchdog timer that monitors microprocessor activity. A timer
circuit is cleared with every low-to-high or high-to-low logic
transition on the watchdog input pin (WDI), which detects pulses
as short as 50 ns. If the timer counts through the preset watchdog
timeout period (t
WD
), a reset is asserted. The microprocessor is
required to toggle the WDI pin to avoid asserting the reset pin.
Failure of the microprocessor to toggle WDI within the timeout
period, therefore, indicates a code execution error, and the reset
pulse generated restarts the microprocessor in a known state.
As well as logic transitions on WDI, the watchdog timer is also
cleared by a reset assertion due to an undervoltage condition on
V
CC
or due to
MR
being pulled low. When a reset asserts, the
watchdog timer clears and does not begin counting again until
the reset deassserts. The watchdog timer can be disabled by
leaving WDI floating or by tristating the WDI driver.
Figure 21. Watchdog Timing Diagram
V
CC
1V
V
CC
0V
V
CC
0V
V
TH
V
TH
0V
V
CC
RESET
RESET
t
RD
t
RD
1V
t
RP
t
RP
11779-020
V
CC
1V
V
CC
0V
V
CC
0V
V
TH
0V
V
CC
WDI
RESET
t
RP
t
RP
t
WD
11779-021
Data Sheet ADM8316/ADM8318/ADM8319/ADM8320/ADM8321/ADM8322
Rev. B | Page 11 of 15
APPLICATIONS INFORMATION
WATCHDOG INPUT CURRENT
To minimize the watchdog input current, leave WDI low for
the majority of the watchdog timeout period. When driven
high, WDI can draw as much as 100 µA. Pulsing WDI low to
high to low at a low duty cycle reduces the effect of the large
input current. When WDI is unconnected, a window comparator
disconnects the watchdog timer from the reset output circuitry
so that a reset is not asserted when the watchdog timer times out.
NEGATIVE GOING V
CC
TRANSIENTS
To avoid unnecessary resets caused by fast power supply transients,
the ADM8316/ADM8318/ADM8319/ADM8320/ADM8321/
ADM8322 are equipped with glitch rejection circuitry. The typical
performance characteristic in Figure 13 plots V
CC
transient
duration vs. reset threshold overdrive. The curves show
combinations of reset threshold overdrive and duration for
which a reset is not generated for 5 V, 4.63 V, and 2.93 V reset
threshold devices. For example, with the 2.93 V threshold, a
transient that goes 100 mV below the threshold and lasts 80 µs
typically does not cause a reset, but if the transient is any larger
in reset threshold overdrive or duration, a reset generates. An
optional 0.1 µF bypass capacitor mounted near V
CC
provides
additional glitch rejection.
ENSURING RESET VALID TO V
CC
= 0 V
Both active low and active high reset outputs are guaranteed to
be valid for V
CC
as low as 0.9 V. However, by using an external
resistor with push-pull configured reset outputs, valid outputs
for V
CC
as low as 0 V are possible. For an active low reset output, a
resistor connected between
RESET
and ground pulls the output
low when it is unable to sink current. For an active high reset
output, a resistor connected between RESET and V
CC
pulls the
output high when it is unable to source current. Use a large
resistance, such as 100 kΩ, so that it does not overload the
reset output when V
CC
is greater than 0.9 V.
Figure 22. Ensuring Reset Valid to V
CC
= 0 V
WATCHDOG SOFTWARE CONSIDERATIONS
In implementing the microprocessor watchdog strobe code, quickly
switching WDI low to high and then high to low (minimizing WDI
high time) is desirable for current consumption reasons. However,
a more effective way of using the watchdog function can be
considered.
A low to high to low WDI pulse within a given subroutine
prevents the watchdog from timing out. However, if the sub-
routine becomes stuck in an infinite loop, the watchdog cannot
detect this because the subroutine continues to toggle WDI. A
more effective coding scheme for detecting this error involves
using a slightly longer watchdog timeout. In the program that
calls the subroutine, WDI is set high. The subroutine sets WDI
low when it is called. If the program executes without error, WDI
is toggled high and low with every loop of the program. If the
subroutine enters an infinite loop, WDI is kept low, the watchdog
times out, and the microprocessor is reset (see Figure 23).
Figure 23. Watchdog Flow Diagram
Figure 24. Typical Application Circuit
ADM8316/
ADM8318/
ADM8319
V
CC
RESET
100kΩ
ADM8318/
ADM8319/
ADM8321/
ADM8322
V
CC
RESET
100kΩ
11779-022
START
SET WDI
HIGH
PROGRAM
CODE
SUBROUTINE
SET WDI
LOW
RETURN
INFINITE LOOP:
WATCHDOG
TIMES OUT
RESET
11779-023
RESET RESET
WDI I/OMR
ADM8316
V
CC
MICROPROCESSOR
11779-024
ADM8316/ADM8318/ADM8319/ADM8320/ADM8321/ADM8322 Data Sheet
Rev. B | Page 12 of 15
OPTIONS
Table 6. Selection Table
Device No. Watchdog Manual Reset
Output Stage
RESET
RESET
ADM8316 Yes Yes Push-pull No
ADM8318 Yes No Push-pull Push-pull
ADM8319 No Yes Push-pull Push-pull
ADM8320 Yes Yes Open-drain No
ADM8321 Yes No Open-drain Push-pull
ADM8322 No Yes Open-drain Push-pull
Table 7. Reset Timeout Options
Suffix Minimum Typical Maximum Unit
A 1 1.4 1.8 ms
B 20 28 36 ms
C
140
200
260
ms
D 1120 1600 2080 ms
Table 8. Watchdog Timeout Options
Suffix Minimum Typical Maximum Unit
W 4.5 6.3 8.1 ms
X 72 102 132 ms
Y 1.12 1.6 2.24 sec
Z 18.0 25.6 33.2 sec
Table 9. Reset Voltage Threshold Options
Reset Threshold Number
T
A
= 25°C
T
A
= −40°C to +125°C
Unit
Minimum
Typical
Maximum
Minimum
Maximum
50
4.950
5.000
5.050
4.925
5.075
V
49
4.851
4.900
4.949
4.826
4.974
V
48
4.752
4.800
4.848
4.728
4.872
V
47
4.653
4.700
4.747
4.629
4.771
V
46
4.584
4.630
4.676
4.560
4.700
V
45
4.455
4.500
4.545
4.432
4.568
V
44
4.346
4.390
4.434
4.324
4.456
V
43
4.257
4.300
4.343
4.235
4.365
V
42
4.158
4.200
4.242
4.137
4.263
V
41
4.059
4.100
4.141
4.038
4.162
V
40
3.960
4.00
4.040
3.940
4.060
V
39
3.861
3.900
3.939
3.841
3.959
V
38
3.762
3.800
3.838
3.743
3.857
V
37
3.663
3.700
3.737
3.644
3.756
V
36
3.564
3.600
3.636
3.546
3.654
V
35
3.465
3.500
3.535
3.447
3.553
V
34
3.366
3.400
3.434
3.349
3.451
V
33
3.267
3.300
3.333
3.250
3.350
V
32
3.168
3.200
3.232
3.152
3.248
V
3N
3.148
3.180
3.212
3.132
3.228
V
31
3.049
3.080
3.111
3.033
3.127
V
30
2.970
3.000
3.030
2.955
3.045
V
29
2.901
2.930
2.959
2.886
2.974
V
28
2.772
2.800
2.828
2.758
2.842
V
27
2.673
2.700
2.727
2.659
2.741
V
26
2.604
2.630
2.656
2.590
2.670
V
25
2.475
2.500
2.525
2.462
2.538
V
P1-P3P4-P6P7-P9P10-P12P13-P15

ADM8321WCY46ARJZR7

Mfr. #:
Buy ADM8321WCY46ARJZR7
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits WD ODb PP 200msTO 1.6sWD 4.63V
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet