ICSSSTUAF32865A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 13
ICSSSTUAF32865A 7097/11
Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)
Simulation Load Circuit
Voltage and Current Waveforms Inputs Active and Inactive
Times
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Setup and Hold Times
Production-Test Load Circuit
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Propagation Delay Times
NOTES:
1. C
L includes probe and jig capacitance.
2. I
DD tested with clock and data inputs held at VDD or GND, and
Io = 0mA
3. All input pulses are supplied by generators having the following
characteristics: PRR ≤10MHz, Zo = 50Ω, input slew rate = 1 V/ns
±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per
measurement.
5. V
TT = VREF = VDD/2
6. V
IH = VREF + 250mV (AC voltage levels) for differential inputs.
V
IH = VDD for LVCMOS input.
7. V
IL = VREF - 250mV (AC voltage levels) for differential inputs.
V
IL = GND for LVCMOS input.
8. V
ID = 600mV.
9. t
PLH and tPHL are the same as tPDM.
CL =30pF
RL =1K
DUT
Out
RL=100
CLK Inputs
T
L =50
T
L =350ps,50
Test Point
CLK
CLK
VDD
RL =1K
Test Point
Test Point
VDD
0V
V
DD/2
LVCMOS
RESET
Input
IDD
VDD/2
tINACT
tACT
10%
90%
VICR
VID
VICR
Input
tW
VREF
VIH
VIL
VREF
Input
VICR
VID
tSU tH
CLK
CLK
ZO =50
Test
Point
RL =50
DUT
Out
CLK Inputs
CLK
VDD/2
CLK
ZO =50
ZO =50
Test
Point
Test
Point
CLK
V
ICR
VID
tPLH tPHL
Output
V
OH
VOL
VICR
VTT VTT
CLK
VOH
VOL
VIH
VIL
tRPHL
VDD/2
V
TT
LVCMOS
RESET
Input
Output
