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MC74VHC86MELG

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 7
1 Publication Order Number:
MC74VHC86/D
MC74VHC86
Quad 2-Input XOR Gate
The MC74VHC86 is an advanced high speed CMOS 2−input
Exclusive−OR gate fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V
systems to 3 V systems.
Features
• High Speed: t
PD
= 4.8 ns (Typ) at V
CC
= 5 V
• Low Power Dissipation: I
CC
= 2 mA (Max) at T
A
= 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model (HBM) > 2000 V;
Machine Model > 200 V
• Chip Complexity: 56 FETs or 14 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Figure 1. Logic Diagram
Y = AęB
3
Y1
1
A1
2
B1
6
Y2
4
A2
5
B2
8
Y3
9
A3
10
B3
11
Y4
12
A4
13
B4
Figure 2. Pinout: 14−Lead Packages (Top View)
1314 12 11 10 9 8
21 34567
V
CC
B4 A4 Y4 B3 A3 Y3
A1 B1 Y1 A2 B2 Y2 GND
MARKING
DIAGRAMS
TSSOP−14
DT SUFFIX
CASE 948G
1
SOIC−14
D SUFFIX
CASE 751A
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
A = Assembly Location
WL, L = Wafer Lot
Y, YY = Year
WW, W = Work Week
G or G = Pb−Free Package
VHC86G
AWLYWW
1
14
VHC
86
ALYWG
G
1
14
(Note: Microdot may be in either location)
1
14
Inputs Output
FUNCTION TABLE
AB Y
L
L
H
H
L
H
L
H
L
H
H
L
MC74VHC86
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2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage –0.5 to +7.0 V
V
in
DC Input Voltage –0.5 to +7.0 V
V
out
DC Output Voltage –0.5 to V
CC
+0.5 V
I
IK
Input Diode Current −20 mA
I
OK
Output Diode Current $20 mA
I
out
DC Output Current, per Pin $25 mA
I
CC
DC Supply Current, V
CC
and GND Pins $50 mA
P
D
Power Dissipation in Still Air, SOIC Package
†
TSSOP Package
†
500
450
mW
T
stg
Storage Temperature –65 to +150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 2.0 5.5 V
V
in
DC Input Voltage 0 5.5 V
V
out
DC Output Voltage 0 V
CC
V
T
A
Operating Temperature, All Package Types −55 +125 °C
t
r
, t
f
Input Rise and Fall Time V
CC
= 3.3 V ±0.3 V
V
CC
= 5.0 V ±0.5 V
0
0
100
20
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74VHC86
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
CC
V
T
A
= 25°C T
A
= −55°C to +125°C
Uni
t
Min Typ Max Min Max
V
IH
High−Level Input
Voltage
2.0
3.0 to
5.5
1.50
V
CC
x 0.7
1.50
V
CC
x 0.7
V
V
IL
Low−Level Input
Voltage
2.0
3.0 to
5.5
0.50
V
CC
x 0.3
0.50
V
CC
x 0.3
V
V
OH
High−Level Output
Voltage
V
in
= V
IH
or V
IL
I
OH
= −50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
V
V
in
= V
IH
or V
IL
I
OH
= −4 mA
I
OH
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
V
OL
Low−Level Output
Voltage
V
in
= V
IH
or V
IL
I
OL
= 50 mA
2.0
3.0
4.5
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
I
in
Input Leakage Current V
in
= 5.5 V or GND 0 to 5.5 ±0.1 ±1.0
mA
I
CC
Quiescent Supply
Current
V
in
= V
CC
or GND 5.5 2.0 20.0
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0ns)
Symbol Parameter Test Conditions
T
A
= 25°C
T
A
= −55°C to
+125°C
Uni
t
Min Typ Max Min Max
t
PLH
,
t
PHL
Propagation Delay, A or B to Y
V
CC
= 3.3 ± 0.3 V C
L
= 15 pF
C
L
= 50 pF
7.0
9.5
11.0
14.5
1.0
1.0
13.0
16.5
ns
V
CC
= 5.0 ± 0.5 V C
L
= 15 pF
C
L
= 50 pF
4.8
6.3
6.8
8.8
1.0
1.0
8.0
10.0
C
in
Input Capacitance 4 10 10 pF
C
PD
Power Dissipation Capacitance (Note 1.)
Typical @ 25°C, V
CC
= 5.0 V
pF
18
1. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/4 (per gate). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0ns, C
L
= 50 pF, V
CC
= 5.0 V, Measured in SOIC Package)
Symbol
Characteristic
T
A
= 25°C
Unit
Typ Max
V
OLP
Quiet Output Maximum Dynamic V
OL
0.3 0.8 V
V
OLV
Quiet Output Minimum Dynamic V
OL
−0.3 −0.8 V
V
IHD
Minimum High Level Dynamic Input Voltage 3.5 V
V
ILD
Maximum Low Level Dynamic Input Voltage 1.5 V
P1-P3P4-P6

MC74VHC86MELG

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Manufacturer:
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Description:
IC GATE XOR 4CH 2-INP 14SOEIAJ
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