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74LVTH322245EC,551

P1-P3P4-P6P7-P9P10-P12
74LVTH322245_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 24 January 2007 7 of 12
NXP Semiconductors
74LVTH322245
3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 5. Input to output propagation delays
mna477
nAn, nBn
input
nBn, nAn
output
t
PHL
t
PLH
GND
V
I
V
M
V
M
V
OH
V
OL
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6. enable and disable times
001aah683
GND
GND
3.0 V
V
OL
V
OH
V
I
V
M
V
M
V
Y
V
X
t
PLZ
t
PZL
t
PHZ
t
PZH
outputs
disabled
outputs
enabled
outputs
enabled
V
M
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOE input
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
M
V
M
V
X
V
Y
2.7 V to 3.6 V 1.5 V 1.5 V V
OL
+ 0.3 V V
OH
− 0.3 V
74LVTH322245_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 24 January 2007 8 of 12
NXP Semiconductors
74LVTH322245
3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state
Test data is given in Table 9.
Definitions test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
V
EXT
= External voltage for measuring switching times.
Fig 7. Load circuitry for switching times
V
EXT
V
CC
V
I
V
O
001aae235
DUT
C
L
R
T
R
L
R
L
PULSE
GENERATOR
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
Table 9. Test data
Input
Load
V
EXT
V
I
f
i
t
W
t
r
, t
f
R
L
C
L
t
PHZ
, t
PZH
t
PLZ
, t
PZL
t
PLH
, t
PHL
2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 500 Ω 50 pF GND 6 V open
74LVTH322245_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 24 January 2007 9 of 12
NXP Semiconductors
74LVTH322245
3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state
12. Package outline
Fig 8. Package outline SOT536-1 (LFBGA96)
0.8
A
1
bA
2
UNIT
D
ye
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
00-03-04
03-02-05
IEC JEDEC JEITA
mm
1.5
0.41
0.31
1.2
0.9
5.6
5.4
y
1
13.6
13.4
0.51
0.41
0.1 0.2
e
1
4
e
2
12
DIMENSIONS (mm are the original dimensions)
SOT536-1
E
0.15
v
0.1
w
0 5 10 mm
scale
SOT536-1
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm
A
max.
A
A
2
A
1
detail X
e
e
X
D
E
A
B
C
D
E
F
H
G
J
K
L
M
P
N
R
T
246135
B
A
e
2
e
1
ball A1
index area
ball A1
index area
y
y
1
C
b
C
AC
C
B
∅ v
M
∅ w
M
1/2 e
1/2 e
P1-P3P4-P6P7-P9P10-P12

74LVTH322245EC,551

Mfr. #:
Buy 74LVTH322245EC,551
Manufacturer:
NXP Semiconductors
Description:
IC TXRX NON-INVERT 3.6V 96LFBGA 74LVTH
Lifecycle:
New from this manufacturer.
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