AOZ1210
Rev. 1.7 December 2009 www.aosmd.com Page 10 of 14
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
where;
C
O
is the output filter capacitor,
R
L
is load resistor value, and
ESR
CO
is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter close loop transfer function to get desired gain
and phase. Several different types of compensation
network can be used for AOZ1210. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1210, FB pin and COMP pin are the inverting
input and the output of internal transconductance error
amplifier. A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
where;
G
EA
is the error amplifier transconductance, which is 200 x 10
-6
A/V,
G
VEA
is the error amplifier voltage
The zero given by the external compensation network,
capacitor C
C
(C5 in Figure 1) and resistor R
C
(R1 in
Figure 1), is located at:
To design the compensation circuit, a target crossover
frequency f
C
for close loop must be selected. The system
crossover frequency is where the control loop has unity
gain. The crossover frequency is also called the
converter bandwidth. Generally a higher bandwidth
means faster response to load transient. However, the
bandwidth should not be too high due to system stability
concern. When designing the compensation loop,
converter stability under all line and load condition must
be considered.
Usually, it is recommended to set the bandwidth to be
less than 1/10 of switching frequency. It is recommended
to choose a crossover frequency less than 30kHz.
The strategy for choosing R
C
and C
C
is to set the cross
over frequency with R
C
and set the compensator zero
with C
C
. Using selected crossover frequency, f
C
, to
calculate R
C
:
where;
f
C
is desired crossover frequency,
V
FB
is 0.8V,
G
EA
is the error amplifier transconductance, which is 200x10
-6
A/V, and
G
CS
is the current sense circuit transconductance, which is
5.64 A/V
The compensation capacitor C
C
and resistor R
C
together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of the selected
crossover frequency. C
C
can is selected by:
The equation above can also be simplified to:
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com
.
Thermal Management and Layout
Consideration
In the AOZ1210 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the V
IN
pin, to the LX
pins, to the filter inductor, to the output capacitor and
load, and then returns to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the GND pin of the
AOZ1210, to the LX pins of the AZO1210. Current flows
in the second loop when the low side diode is on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is recommended to connect input capacitor, output
capacitor, and GND pin of the AOZ1210.
In the AOZ1210 buck regulator circuit, the three major
power dissipating components are the AOZ1210,
external diode and output inductor. The total power
f
Z1
1
2π C
O
ESR
CO
××
------------------------------------------------
=
f
p2
G
EA
2π C
C
G
VEA
××
------------------------------------------ -
=
f
Z2
1
2π C
C
R
C
××
-----------------------------------
=
f
C
30kHz=
R
C
f
C
V
O
V
FB
----------
2π C
O
×
G
EA
G
CS
×
----------------------------- -
××=
C
C
1.5
2π R
C
f
p1
××
-----------------------------------
=
C
C
C
O
R
L
×
R
C
---------------------
=
