CY2318ANZPVC-11

CY2318ANZ
Document #: 38-07181 Rev. *C Page 4 of 9
Maximum Ratings
Supply Voltage to Ground Potential..................–0.5 to +7.0V
DC Input Voltage (except BUF_IN).......... –0.5V to V
DD
+ 0.5
DC Input Voltage (BUF_IN).............................. –0.5V to 7.0V
Storage Temperature.................................. –65°C to +150°C
Junction Temperature............................................... +150°C
Static Discharge Voltage............................................>2000V
(per MIL-STD-883, Method 3015)
Operating Conditions
Parameter Description Min. Max. Unit
V
DD
, V
DDIIC
Supply Voltage 3.135 3.465 V
T
A
Operating Temperature (Ambient Temperature) 0 70 °C
C
L
Load Capacitance 20 30 pF
C
IN
Input Capacitance 7 pF
t
PU
Power-up time for all V
DD
s to reach minimum specified voltage
(power ramps must be monotonic)
0.05 50 ms
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
V
IL
Input LOW Voltage
[2]
For all pins except serial
interface pins
0.8 V
V
ILiic
Input LOW Voltage For serial pins only 0.7 V
V
IH
Input HIGH Voltage
[2]
2.0 V
I
IL
Input LOW Current
(BUF_IN input)
V
IN
= 0V –10 10 µA
I
IL
Input LOW Current
(Except BUF_IN Pin)
V
IN
= 0V 100 µA
I
IH
Input HIGH Current V
IN
= V
DD
–10 10 µA
V
OL
Output LOW Voltage
[3]
I
OL
= 25 mA 0.4 V
V
OH
Output HIGH Voltage
[3]
I
OH
= –36 mA 2.4 V
I
DD
Supply Current
[3]
Unloaded outputs, 100 MHz 200 mA
I
DD
Supply Current Loaded outputs, 100 MHz 360 mA
I
DD
Supply Current
[3]
Unloaded outputs, 66.67 MHz 150 mA
I
DD
Supply Current Loaded outputs, 66.67 MHz 230 mA
I
DDS
Supply Current BUF_IN = V
DD or
V
SS,
all other inputs at V
DD
500 µA
Notes:
2. BUF_IN input has a threshold voltage of V
DD
/2.
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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CY2318ANZ
Document #: 38-07181 Rev. *C Page 5 of 9
Switching Characteristics
[4]
Parameter Name Test Conditions Min. Typ. Max. Unit
Maximum Operating Frequency 100 MHz
Duty Cycle
[3, 5]
= t
2
÷ t
1
Measured at 1.5V 45.0 50.0 55.0 %
t
3
Rising Edge Rate
[3]
Measured between 0.4V and 2.4V 0.9 1.5 4.0 V/ns
t
4
Falling Edge Rate
[3]
Measured between 2.4V and 0.4V 0.9 1.5 4.0 V/ns
t
5
Output to Output Skew
[3]
All outputs equally loaded 150 250 ps
t
6
SDRAM Buffer LH Prop. Delay
[3]
Input edge greater than 1 V/ns 1.0 3.5 5.0 ns
t
7
SDRAM Buffer HL Prop. Delay
[3]
Input edge greater than 1 V/ns 1.0 3.5 5.0 ns
t
8
SDRAM Buffer Enable Delay
[3]
Input edge greater than 1 V/ns 1.0 5 12 ns
t
9
SDRAM Buffer Disable Delay
[3]
Input edge greater than 1 V/ns 1.0 20 30 ns
Switching Waveforms
Notes:
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
Duty Cycle Timing
t
1
t
2
1.5V 1.5V 1.5V
All Outputs Rise/Fall Time
OUTPUT
t
3
3.3V
0V
0.4V
2.4V 2.4V
0.4V
t
4
Output-Output Skew
1.5V
t
5
OUTPUT
OUTPUT
1.5V
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CY2318ANZ
Document #: 38-07181 Rev. *C Page 6 of 9
Switching Waveforms (continued)
SDRAM Buffer LH and HL Propagation Delay
t
6
INPUT
OUTPUT
t
7
t
8
OE
OUTPUTS
SDRAM Buffer Enable and Disable Times
t
9
Three-State
Active
0.1 µF
V
DD
CLK out
C
LOAD
OUTPUTS
GND
Test Circuit
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CY2318ANZPVC-11

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Clock Buffer 3.3V Buffer COM
Lifecycle:
New from this manufacturer.
Delivery:
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