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CY2318ANZPVXC-11T

P1-P3P4-P6P7-P9
18 Output, 3.3V SDRAM Buffer fo
r
Desktop PCs with 4 DIMMs
CY2318ANZ
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07181 Rev. *C Revised Oct. 03, 2005
Features
• One input to 18 output buffer/driver
• Supports up to four SDRAM DIMMs
• Two additional outputs for feedback
• Serial interface for individual output control
• 150ps typical output-output skew
• Up to 100 MHz operation
• Dedicated OE pin for testing
• Space-saving 48-pin SSOP package
• 3.3V operation
Functional Description
The CY2318ANZ is a 3.3V buffer designed to distribute
high-speed clocks in PC applications. The part has 18 outputs,
16 of which can be used to drive up to four SDRAM DIMMs,
and the remaining can be used for external feedback to a PLL.
The device operates at 3.3V and outputs can run up to 100
MHz, thus making it compatible with Pentium II
®
processors.
The CY2318ANZ can be used in conjunction with the CY2280,
CY2281, CY2282 or similar clock synthesizer for a complete
Pentium II motherboard solution.
The CY2318ANZ also includes a serial interface which can
enable or disable each output clock. On power-up, all output
clocks are enabled (internal pull up). A separate Output
Enable pin facilitates testing on ATE.
Block Diagram
Serial Interface
BUF_IN
SDATA
SCLOCK
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
1
2
3
4
NC
NC
V
DD
SDRAM15
SDRAM14
V
SS
V
DD
SDRAM13
SSOP
Top View
Pin Configuration
Decoding
8
5
6
7
12
9
10
11
13
14
15
16
20
17
18
19
24
21
22
23
48
47
46
45
41
44
43
42
37
40
39
38
36
35
34
33
29
32
31
30
25
28
27
26
SDRAM12
V
SS
OE
V
DD
SDRAM11
SDRAM10
V
SS
V
DD
SDRAM9
SDRAM8
V
SS
V
DD
SDRAM17
V
SS
V
SSIIC
SCLOCK
NC
NC
V
DD
SDRAM0
SDRAM1
V
SS
V
DD
SDRAM2
V
SS
BUF_IN
V
DD
SDRAM4
SDRAM5
V
SS
V
DD
SDRAM6
SDRAM7
V
SS
V
DD
SDRAM16
V
SS
V
DDIIC
SDATA
SDRAM3
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SDRAM13
SDRAM14
SDRAM15
SDRAM16
SDRAM17
OE
[+] Feedback
CY2318ANZ
Document #: 38-07181 Rev. *C Page 2 of 9
Device Functionality
Pin Summary
Name Pins Description
V
DD
3, 7, 12, 16, 20, 29, 33, 37, 42, 46 3.3V Digital voltage supply
V
SS
6, 10, 15, 19, 22, 27, 30, 34, 39, 43 Ground
V
DDIIC
23 Serial interface voltage supply
V
SSIIC
26 Ground for serial interface
BUF_IN 11 Input clock (5V Tolerant)
OE 38 Output Enable (active HIGH), Three-state outputs when low
[1]
SDATA 24 Serial data input
[1]
SCLK 25 Serial clock input
[1]
SDRAM [0–3] 4, 5, 8, 9 SDRAM byte 0 clock outputs
SDRAM [4–7] 13, 14, 17, 18 SDRAM byte 1 clock outputs
SDRAM [8–11] 31, 32, 35, 36 SDRAM byte 2 clock outputs
SDRAM [12–15] 40, 41, 44, 45 SDRAM byte 3 clock outputs
SDRAM [16–17] 21, 28 SDRAM clock outputs usable for feedback
N/C 1, 2, 47, 48 Reserved for future modifications, do not connect in system
Note:
1. Internal pull-up resistor to V
DD
(value > 100 kohms)
OE SDRAM [0–17]
0 Hi-Z
1 1 x BUF_IN
[+] Feedback
CY2318ANZ
Document #: 38-07181 Rev. *C Page 3 of 9
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
• Serial interface address for the CY2318ANZ is:
•
•
•
•
A6 A5 A4 A3 A2 A1 A0 R/W
1101001----
Byte 0:SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit Pin # Description
Bit 7 18 SDRAM7 (Active/Inactive)
Bit 6 17 SDRAM6 (Active/Inactive)
Bit 5 14 SDRAM5 (Active/Inactive)
Bit 4 13 SDRAM4 (Active/Inactive)
Bit 3 9 SDRAM3 (Active/Inactive)
Bit 2 8 SDRAM2 (Active/Inactive)
Bit 1 5 SDRAM1 (Active/Inactive)
Bit 0 4 SDRAM0 (Active/Inactive)
Byte 1: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit Pin # Description
Bit 7 45 SDRAM15 (Active/Inactive)
Bit 6 44 SDRAM14 (Active/Inactive)
Bit 5 41 SDRAM13 (Active/Inactive)
Bit 4 40 SDRAM12 (Active/Inactive)
Bit 3 36 SDRAM11 (Active/Inactive)
Bit 2 35 SDRAM10 (Active/Inactive)
Bit 1 32 SDRAM9 (Active/Inactive)
Bit 0 31 SDRAM8 (Active/Inactive)
Byte 2: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit Pin # Description
Bit 7 28 SDRAM17 (Active/Inactive)
Bit 6 21 SDRAM16 (Active/Inactive)
Bit 5 -- Reserved, drive to 0
Bit 4 -- Reserved, drive to 0
Bit 3 -- Reserved, drive to 0
Bit 2 -- Reserved, drive to 0
Bit 1 -- Reserved, drive to 0
Bit 0 -- Reserved, drive to 0
[+] Feedback
P1-P3P4-P6P7-P9

CY2318ANZPVXC-11T

Mfr. #:
Buy CY2318ANZPVXC-11T
Manufacturer:
Cypress Semiconductor
Description:
Clock Buffer 3.3V Buffer COM
Lifecycle:
New from this manufacturer.
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