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CYWB0226ABM-BVXI

P1-P3P4-P6P7-P7
CYWB0224ABS, CYWB0224ABM
CYWB0226ABS, CYWB0226ABM
PRELIMINARY
CONFIDENTIAL
Page 4 of 7
Pin Assignments
Table 1. Astoria Pin Assignments
Pin Name
Pin De-
scription
Power
Domain
P-Port
PCRAM Non
Multiplexing
IO PCRAM
Multiplexing
(ADM)
IO SRAM IO PNAND IO SPI IO
CLK (pull low
in Asyn mode)
I CLK (pull -low in
Async mode)
I Ext pull low I Ext pull low I SCK I Clock
PVDDQ
VGND
CE# I CE# I CE# I CE# I SS# I Chip
Enable/PNA
ND Chip
Select/SPI
Slave Select
A0 I Ext pull-up I A0 I CLE I Ext pull-up I Addr. Bus
0/PNAND
Command
Latch
A1 I Ext pull-up I A1 I RB# O Ext pull-up I Addr. Bus
1/PNAND
Ready_Buy
A[3:2] I A[2] = 1
A[3] = don’t
care
I A[3:2] I A[3:2] = 00 I A[3:2] = 10 I Addr. Bus
[3:2]
A4 I Ext pull-up I A4 I WP# I Ext pull-up I Addr. Bus
4/PNAND
Write
Protect
A5 I SCL IO A5 I SCL IO SCL IO Addr. Bus
5/I2C clock
A6 I SDA IO A6 I SDA IO SDA IO Addr. Bus
6/I2C data
A7 I Ext pull-up I A7 I A7 => 1:SBD
A7 => 0: LBD
I Ext pull-up I Addr. Bus 7
DQ[0] IO AD[0] IO DQ[0] IO IO[0] IO SDI I SPI
Input/Data
Bus 0
DQ[1] IO AD[1] IO DQ[1] IO IO[1] IO SDO O SPI
Output/Data
Bus 1
DQ[15:2] IO AD[15:2] IO DQ[15:2] IO IO[15:2] IO Ext pull-up I Data Bus
ADV# I ADV# I I ALE I Ext pull-up I Address
Valid
OE# I OE# I OE# I RE# I Ext pull-up I Output
Enable
WE# I WE# I WE# I WE# I Ext pull-up I Write
Enable
DRQ &
Int
INT# O INT# O INT# O INT# O SINT# O Interrupt
Request
GVDDQ
VGND
DRQ# O DRQ# O DRQ# O DRQ# O N/C O DMA
Request
DACK# I DACK# I DACK# I DACK# I Ext pull-up I DMA
Acknowl-
edgement
U-Port
D+ IO/Z USB D+
UVDDQ
UVSSQ
D- IO/Z USB D-
SWD+ IO/Z USB Switch
DP
SWD- IO/Z USB Switch
DM
[+] Feedback
CYWB0224ABS, CYWB0224ABM
CYWB0226ABS, CYWB0226ABM
PRELIMINARY
CONFIDENTIAL
Page 5 of 7
S-Port
SDIO & NAND
Configuration
IO
NAND only
Configuration
IO
Double SDIO
Configuration
IO
NAND & GPIO
Configuration
IO
SDIO & GPIO
Configuration
IO
GPIO only
Configuration
IO
SD_D[7:0] IO NAND_IO[15:8]
or PD[7:0]
(GPIO)
IO SD_D[7:0] IO NAND_IO[15:8]
or
PD[7:0] (GPIO)
IO SD_D[7:0] IO PD[7:0] (GPIO) IO SD Data
bus/NAND
Upper IO
bus
SSVD-
DQ
VGND
SD_CLK O NAND_CE8# or
NAND_R/B4#
O
I
SD_CLK O PC-7 (GPIO) or
NAND_CE8# or
NAND_R/B4#
IO
O
I
SD_CLK PC-7 (GPIO) IO SD Clock,
NAND CE8#
or NAND
R/B4#
SD_CMD IO NAND_CE7# or
NAND_R/B3#
O
I
SD_CMD IO PC-3 (GPIO) or
NAND_CE7# or
NAND_R/B3#
IO
O
I
SD_CMD IO PC-3 (GPIO) IO SD
Command,
NAND CE7#
or NAND
R/B4#
SD_POW O NAND_CE6# O SD_POW PC-6 (GPIO) or
NAND_CE6#
IO
O
SD_POW PC-6 (GPIO) IO SD Power
Control/NA
ND CE6#
SD_WP I NAND_CE5# O SD_WP I PC-5 (GPIO) or
NAND_CE5#
IO SD_WP I N/C I GPIO (SD
Write
Protection
Microswitch
) or NAND
CE5#
NAND_IO[7:0] IO NAND_IO[7:0] IO SD2_D[7:0] IO NAND_IO[7:0] O PB[7:0] (GPIO) IO PB[7:0] (GPIO) IO NAND
Lower IO
bus
SNVD-
DQ
VGND
NAND_CLE O NAND_CLE O SD2_CLK O NAND_CLE O PA-6 (GPIO) IO PA-6 (GPIO) IO CMD Latch
Enable
NAND_ALE O NAND_ALE O SD2_CMD IO NAND_ALE O PA-7 (GPIO) IO PA-7 (GPIO) IO Address
Latch
Enable
NAND_CE# O NAND_CE# O SD2_POW O NAND_CE# O PC-0 (GPIO) IO PC-0 (GPIO) IO Chip Enable
NAND_RE# O NAND_RE# O N/C O NAND_RE# O N/C O N/C O Read
Enable
NAND_WE# O NAND_WE# O N/C O NAND_WE# O N/C O N/C O Write
Enable
NAND_WP# O NAND_WP# O PA-5 (GPIO) IO NAND_WP# I PA-5 (GPIO) IO PA-5 (GPIO) IO Write
Protect
NAND_R/B# I NAND_R/B# I N/C I NAND_R/B# I N/C I N/C I Ready/Busy
NAND_CE2# O NAND_CE2# O SD2_WP O NAND_CE2# O PC-2 (GPIO) IO PC-2 (GPIO) IO Chip Enable
2
Other
RESETOUT /
NAND_R/B2#
O
I
NAND_R/B2# I RESETOUT O RESETOUT or
NAND_R/B2#
0
I
RESETOUT O RESETOUT O RESET
OUT or
NAND
Busy/Ready
GVDDQ
VGND
PC-4
(GPIO[0]) /
SD_CD /
NAND_CE4#
IO
I
O
NAND_CE4# O PC-4 (GPIO[0])
/
SD_CD
IO
I
PC-4 (GPIO[0])
or
NAND_CE4#
IO
O
PC-4 (GPIO[0])
or
SD_CD
IO
I
PC-4 (GPIO[0]) IO General
Input/Output
0 or
SD/MMC
Card
Detection or
NAND CE4#
PC-5
(GPIO[1]) /
NAND_CE3#
IO
O
NAND_CE3# O PC-5 (GPIO[1])
/
SD2_CD
IO
I
PC-5 (GPIO[1])
or
NAND_CE3#
IO
O
PC-5 (GPIO[1]) IO PC-5 (GPIO[1]) IO General
Input/Output
1,
NAND
CE3#, or
SD2_CD
RESET# I RESET
WAKEUP I Wake Up
Signal
Conf
XTALSLC[1:0] I Clock Select
0 and 1
GVDDQ
VGND
TEST[2:0] I Test Config-
uration
Clock
XTALIN I Crystal/Cloc
k IN
XVDDQ
VGND
XTALOUT O Crystal Out
Table 1. Astoria Pin Assignments (continued)
[+] Feedback
CYWB0224ABS, CYWB0224ABM
CYWB0226ABS, CYWB0226ABM
PRELIMINARY
CONFIDENTIAL
Page 6 of 7
Power
PVDDQ Power Processor
I/F VDD
SNVDDQ Power NAND VDD
UVDDQ Power USB VDD
SSVDDQ Power SDIO VDD
GVDDQ Power Misc IO
VDD
AVDDQ Power Analog VDD
XVDDQ Power Crystal VDD
VDD Power Core VDD
VDD33 Power Independen
t 3.3V
UVSSQ Power USB GND
AVSSQ Power Analog GND
VGND Power Core GND
Ordering Information
Ordering Code Package Type NAND Flash Support
Available Clock Input
Frequencies (MHz)
CYWB0224ABS-BVXI 100 VFBGA – Pb-Free Support SLC NAND Flash only 19.2, 24, 26, 48
CYWB0224ABM-BVXI 100 VFBGA – Pb-Free Support SLC and MLC NAND Flash 19.2, 24, 26, 48
CYWB0226ABS-BVXI 100 VFBGA – Pb-Free Support SLC NAND Flash and USB
switch
19.2, 24, 26, 48
CYWB0226ABM-BVXI 100 VFBGA – Pb-Free Support SLC and MLC NAND Flash and
USB switch
19.2, 24, 26, 48
Table 1. Astoria Pin Assignments (continued)
[+] Feedback
P1-P3P4-P6P7-P7

CYWB0226ABM-BVXI

Mfr. #:
Buy CYWB0226ABM-BVXI
Manufacturer:
Cypress Semiconductor
Description:
USB Interface IC USB/Mass Storage
Lifecycle:
New from this manufacturer.
Delivery:
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