IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 9 ©2014 Integrated Device Technology, Inc.
IDT8T49N008I Data Sheet PROGRAMMABLE FEMTOCLOCK
®
NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS
Power-up Default Configuration Description
The IDT8T49N008I supports a variety of options such as different
output styles, number of programmed default frequencies, output en-
able and operating temperature range. The device options and de-
fault frequencies must be specified at the time of order and are
programmed by IDT prior to shipment. The document, Programma-
ble FemtoClock
®
NG Product Ordering Guide specifies the available
order codes, including the device options and default frequency con-
figurations. Example part number: 8T49N004A-007NLGI, specifies a
quad frequency clock generator with default frequencies of
106.25MHz, 133.333MHz, 156.25MHz and 156.25MHz, with four
LVDS outputs that are enabled after power-up, specified over the in-
dustrial temperature range and housed in a lead-free (6/6 RoHS)
VFQFN package.
Other order codes with respective programmed frequencies are
available from IDT upon request. After power-up changes to the
output frequencies are controlled by FSEL[1:0] or the I
2
C interface.
Changes to the output styles and states of outputs (enabled or
disabled) can also be controlled with the I
2
C interface after power up.
Table 3H. Power-up Default Settings
Serial Interface Configuration Description
The IDT8T49N008I has an I
2
C-compatible configuration interface to
access any of the internal registers (Table 3B) for frequency and PLL
parameter programming. The IDT849N008I acts as a slave device on
the I
2
C bus and has the address 0b110111x, where x is set by the
value on the ADDR_SEL input (see Tables 3I and 3J). The interface
accepts byte-oriented block write and block read operations. An
address byte (P) specifies the register address (Table 3B) as the byte
position of the first register to write or read. Data bytes (registers) are
accessed in sequential order from the lowest to the highest byte
(most significant bit first, see Table 3K, 3L). Read and write block
transfers can be stopped after any complete byte transfer. It is
recommended to terminate the I
2
C read or write transfer after
accessing byte #23 by sending a stop command.
For full electrical I
2
C compliance, it is recommended to use external
pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 50k typical.
Table 3I. I
2
C Device Slave Address ADDR_SEL = 0 (default)
Table 3J. I
2
C Device Slave Address ADDR_SEL = 1
Table 3K. Block Write Operation
Table 3L. Block Read Operation
FSEL1 FSEL0 Frequency
PLL State
(On or Bypass)
Output State
(Active or High Impedance)
Output Style
(LVDS or LVPECL)
0 (default) 0 (default) Frequency 0 PLL State 0 Output State 0 Output Style 0
0 1 Frequency 1 PLL State 1 Output State 1 Output Style 1
1 0 Frequency 2 PLL State 2 Output State 2 Output Style 2
1 1 Frequency 3 PLL State 3 Output State 3 Output Style 3
1101110R/W
1101111R/W
Bit 1 2:8 9 10 11:18 19 20:27 28 29-36 37 ... ... ...
Description
START Slave Address W (0) ACK Address Byte P ACK
Data Byte
(P)
ACK
Data Byte
(P+1)
ACK
Data Byte
...
ACK STOP
Length (bits) 1711818181811
Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39-46 47 ... ... ...
Description
START
Slave
Address
W
(0)
A
C
K
Address
byte P
A
C
K
Repeated
START
Slave
address
R
(1)
A
C
K
Data Byte
(P)
A
C
K
Data Byte
(P+1)
A
C
K
Data Byte
...
A
C
K
STOP
Length (bits) 1711811 7118181811
