IDT8T49N008ANLGI REVISION A FEBRUARY 13, 2014 3 ©2014 Integrated Device Technology, Inc.
IDT8T49N008I Data Sheet PROGRAMMABLE FEMTOCLOCK
®
NG LVPECL/LVDS CLOCK GENERATOR WITH 8-OUTPUTS
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2 Q0, nQ0 Output Differential output pair. LVPECL or LVDS interface levels.
3, 4 Q1, nQ1 Output Differential output pair. LVPECL or LVDS interface levels.
5, 26 V
CCO
Power Output supply pins.
6, 7 Q2, nQ2 Output Differential output pair. LVPECL or LVDS interface levels.
8, 9 Q3, nQ3 Output Differential output pair. LVPECL or LVDS interface levels.
10, 13, 18,
21, 31, 34,
37, 40
V
EE
Power Negative supply pins.
11,
12
XTAL_IN
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Crystal frequency is selected from Table 3A.
14 CLK Input Pulldown Non-inverting differential clock input.
15 nCLK Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to V
CC
/2.
16,
20
FSEL0,
FSEL1
Input Pulldown
Frequency and configuration. Selects between one of four factory
programmable power-up default configurations. The four configurations can
have different PLL states, output frequencies, output styles and output states.
These default configurations can be overwritten after power-up via I
2
C.
LVCMOS/LVTTL interface levels.
00 = Configuration 0 (default)
01 = Configuration 1
10 = Configuration 2
11 = Configuration 3
17 ADDR_SEL Input Pulldown I
2
C Address select pin. LVCMOS/LVTTL interface levels.
19, 38 V
CC
Power Core supply pins.
22, 23 nQ7, Q7 Output Differential output pair. LVPECL or LVDS interface levels.
24, 25 nQ6, Q6 Output Differential output pair. LVPECL or LVDS interface levels.
27, 28 nQ5, Q5 Output Differential output pair. LVPECL or LVDS interface levels.
29, 30 nQ4, Q4 Output Differential output pair. LVPECL or LVDS interface levels.
32 SCLK Input Pullup I
2
C Clock Input. LVCMOS/LVTTL interface levels.
33 SDATA Input/Output Pullup I
2
C Data Input. Input: LVCMOS/LVTTL interface levels. Output: Open Drain.
35 V
CCA
Power Analog supply pin.
36 LOCK Output PLL Lock Indicator. LVCMOS/LVTTL interface levels.
39 CLK_SEL Input Pulldown
Input source control pin. LVCMOS/LVTTL interface levels.
0 = XTAL (default)
1 = CLK, nCLK
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 3.5 pF
R
PULLDOWN
Input Pulldown Resistor 51 k
R
PULLUP
Input Pullup Resistor 51 k
