EP2AGX45DF25C6G Datasheet EP2AGX260EF29I5G, EP2AGX260FF35I5G, EP2AGX95EF29C5G | P4-P6

1–4 Chapter 1: Overview for the Arria II Device Family

Arria II Device Feature

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation

Table 1–2 and Table 1–3 list the Arria II device package options and user I/O pin

counts, high-speed LVDS channel counts, and transceiver channel counts for Ultra

FineLine BGA (UBGA) and FineLine BGA (FBGA) devices.

Table 1–2. Package Options and I/O Information for Arria II GX Devices (Note 1), (2), (3), (4), (5), (6), (7)

Device

358-Pin Flip Chip UBGA

17 mm x 17 mm

572-Pin Flip Chip FBGA

25 mm x 25 mm

780-Pin Flip Chip FBGA

29 mm x 29 mm

1152-Pin Flip Chip FBGA

35 mm x 35 mm

I/O LVDS (8)

XCVRs

I/O LVDS (8)

XCVRs

I/O LVDS (8)

XCVRs

I/O LVDS (8)

XCVRs

EP2AGX45 156

33(R

or eTX)

+ 32(RX, TX,

or eTX)

4 252

57(R

eTX) +

56(RX, TX,

or eTX)

8 364

85(R

or eTX)

+ 84(RX, TX,

or eTX)

8———

EP2AGX65 156

33(R

or eTX)

+ 32(RX, TX,

or eTX)

4 252

57(R

eTX) +

56(RX, TX,

or eTX)

8 364

85(R

or eTX)

+84(RX,TX,

eTX)

8———

EP2AGX95 — — — 260

57(R

eTX) +

56(RX, TX,

or eTX)

8 372

85(R

or eTX)

+84(RX, TX, or

eTX)

12 452

105(R

eTX) +

104(RX, TX, or

eTX)

EP2AGX125 — — — 260

57(R

eTX) +

56(RX,TX, or

eTX)

8 372

85(R

or eTX)

+84(RX,TX, or

eTX)

12 452

105(R

eTX) +

104(RX, TX, or

eTX)

EP2AGX190 — — — — — — 372

85(R

or eTX)

+84(RX, TX, or

eTX)

12 612

145(R

eTX) +

144(RX, TX, or

eTX)

EP2AGX260 — — — — — — 372

85(R

, eTX)

+84(RX, TX, or

eTX)

12 612

145(R

, eTX) +

144(RX, TX, or

eTX)

Notes to Table 1–2:

(1) The user I/O counts include clock pins.

(2) The arrows indicate packages vertical migration capability. Vertical migration allows you to migrate to devices whose dedicated pins, configuration pins,

and power pins are the same for a given package across device densities.

(3) R

= True LVDS input buffers with on-chip differential termination (R

OCT) support.

(4) RX = True LVDS input buffers without R

OCT support.

(5) TX = True LVDS output buffers.

(6) eTX = Emulated-LVDS output buffers, either

LVDS_E_3R

LVDS_E_1R

(7) The LVDS channel count does not include dedicated clock input pins and PLL clock output pins.

(8) These numbers represent the accumulated LVDS channels supported in Arria II GX row and column I/O banks.

Chapter 1: Overview for the Arria II Device Family 1–5

Arria II Device Feature

July 2012 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration

Arria II devices are available in up to four speed grades: –3 (fastest), –4, –5, and –6

(slowest). Table 1–4 lists the speed grades for Arria II devices.

Table 1–3. Package Options and I/O Information for Arria II GZ Devices (Note 1), (2), (3), (4), (5)

Device

780-Pin Flip Chip FBGA

29 mm x 29 mm

1152-Pin Flip Chip FBGA

35 mm x 35 mm

1517-Pin Flip Chip FBGA

40 mm x 40 mm

I/O LVDS (6)

XCVRs

I/O LVDS (7)

XCVRs

I/O LVDS (7)

XCVRs

EP2AGZ225 — — — 554

135 (RX or eTX) +

140 (TX or eTX)

16 734

179 (RX or eTX) +

184 (TX or eTX)

EP2AGZ300 281

68 (RX or eTX) +

72 eTX

16 554

135 (RX or eTX) +

140 (TX or eTX)

16 734

179 (RX or eTX) +

184 (TX or eTX)

EP2AGZ350 281

68 (RX or eTX) +

72 eTX

16 554

135 (RX or eTX) +

140 (TX or eTX)

16 734

179 (RX or eTX) +

184 (TX or eTX)

Notes to Table 1–3:

(1) The user I/O counts include clock pins.

(2) RX = True LVDS input buffers without R

OCT support for row I/O banks, or true LVDS input buffers without R

OCT support for column I/O

banks.

(3) eTX = Emulated-LVDS output buffers, either

LVDS_E_3R

LVDS_E_1R.

(4) The LVDS RX and TX channels are equally divided between the left and right sides of the device.

(5) The LVDS channel count does not include dedicated clock input pins.

(6) For Arria II GZ 780-pin FBGA package, the LVDS channels are only supported in column I/O banks.

(7) These numbers represents the accumulated LVDS channels supported in Arria II GZ device row and column I/O banks.

Table 1–4. Speed Grades for Arria II Devices

Device

358-Pin Flip Chip

UBGA

572-Pin Flip Chip

FBGA

780-Pin Flip Chip

FBGA

1152-Pin Flip Chip

FBGA

1517-Pin Flip Chip

FBGA

EP2AGX45 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 — —

EP2AGX65 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 — —

EP2AGX95 — C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 —

EP2AGX125 — C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 —

EP2AGX190 — — C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 —

EP2AGX260 — — C4, C5, C6, I3, I5 C4, C5, C6, I3, I5 —

EP2AGZ225 — — — C3, C4, I3, I4 C3, C4, I3, I4

EP2AGZ300 — — C3, C4, I3, I4 C3, C4, I3, I4 C3, C4, I3, I4

EP2AGZ350 — — C3, C4, I3, I4 C3, C4, I3, I4 C3, C4, I3, I4

1–6 Chapter 1: Overview for the Arria II Device Family

Arria II Device Architecture

Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation

Arria II Device Architecture

Arria II devices include a customer-defined feature set optimized for cost-sensitive

applications and offer a wide range of density, memory, embedded multiplier, I/O,

and packaging options. Arria II devices support external memory interfaces and I/O

protocols required by wireless, wireline, broadcast, computer, storage, and military

markets. They inherit the 8-input ALM, M9K and M144K embedded RAM block, and

high-performance DSP blocks from the Stratix

IV device family with a

cost-optimized I/O cell and a transceiver optimized for 6.375 Gbps speeds.

Figure 1–1 and Figure 1–2 show an overview of the Arria II GX and Arria II GZ device

architecture, respectively.

Figure 1–1. Architecture Overview for Arria II GX Devices

Arria II GX FPGA Fabric

(Logic Elements, DSP,

Embedded Memory, Clock Networks)

All the blocks in this graphic are for the largest density in the

Arria II GX family. The number of blocks can vary based on

the density of the device.

PLL

DLL

PLL

Transceiver

Blocks

Plug and Play PCIe hard IP

1, 2,

4, and

High-Speed Differential I/O,

General Purpose I/O, and

Memory Interface

High-Speed Differential I/O,

General Purpose I/O, and

Memory Interface

High-Speed Differential I/O,

General Purpose I/O, and

Memory Interface

High-Speed

Differential I/O

with DPA,

General

Purpose

I/O, and

Memory

Interface

High-Speed

Differential I/O

with DPA,

General

Purpose

I/O, and

Memory

Interface

High-Speed Differential I/O,

General Purpose I/O, and

Memory Interface

××

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EP2AGX45DF25C6G

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Description:

FPGA - Field Programmable Gate Array

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